Compensatory Memory System
First Claim
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1. An compensatory memory system with voltage scaling, comprising:
- a clock generator for transmitting a second clock signal in response to receiving the first clock signal;
a first decode logic block for receiving a first group of addresses associated with data storage locations and the second clock signal, the first decode logic block operative for transmitting a second group of addresses in response to receiving the first group of addresses;
a compensatory delay device coupled for receiving the second clock signal and operative for transmitting an enable signal;
wherein the compensatory delay device is designed using a slow process corner and the compensatory memory system with voltage scaling has increased performance by compensating for logic delays an amplifier trigger speed.
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Abstract
A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.
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Citations
15 Claims
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1. An compensatory memory system with voltage scaling, comprising:
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a clock generator for transmitting a second clock signal in response to receiving the first clock signal; a first decode logic block for receiving a first group of addresses associated with data storage locations and the second clock signal, the first decode logic block operative for transmitting a second group of addresses in response to receiving the first group of addresses; a compensatory delay device coupled for receiving the second clock signal and operative for transmitting an enable signal; wherein the compensatory delay device is designed using a slow process corner and the compensatory memory system with voltage scaling has increased performance by compensating for logic delays an amplifier trigger speed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An compensatory memory system with voltage scaling, comprising:
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a register for storing a plurality of addresses for identifying a plurality of bits; a decoder adapted to be coupled for receiving the addresses and a clock signal; a compensatory delay device coupled to receive the clock signal and transmit an enable signal; an amplifier coupled to transmit a data signal in response receiving the enable signal, wherein the compensatory delay device is designed using a slow process corner and the compensatory memory system with voltage scaling has increased performance by compensating for a maximum trigger speed of the amplifier and a delay associated with a tracking element.
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10. A method for designing an compensatory memory system having a word line and a bit line, steps of the method comprising:
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selecting optimal decode logic based on a slow process corner; determining word line characteristics; determining bit line characteristics; determining sense amplifier trigger characteristics; defining an optimized delay; creating a delay device with the optimized delay; determining an compensatory delay that compensates for the maximum timing characteristic of the word line, bit line, and the maximum trigger speed; and adding a delay margin when the compensatory delay does not meet desired performance standard. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification