Backside Process for a Substrate

• US 20100267217A1
• Filed: 01/11/2010
• Published: 10/21/2010
• Est. Priority Date: 04/20/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiou, Wen-Chih, Wu, Weng-Jin, Yang, Ku-Feng, Hu, Jung-Chih
• Granted Patent: US 8,691,664 B2
• Time in Patent Office: Days
• US Class Current: 438/459
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method of forming a semiconductor device is presented. A conductor is embedded within a substrate, wherein the substrate contains a non-conducting material. The backside of the substrate is ground to a thickness wherein at least 1 μm of the non-conducting material remains on the backside covering the conductor embedded within the substrate. Chemical mechanical polishing (CMP) is employed with an undiscerning slurry to the backside of the substrate, thereby planarizing the substrate and exposing the conductive material. A spin wet-etch, with a protective formulation, is employed to remove a thickness y of the non-conducting material from the backside of the substrate, thereby causing the conductive material to uniformly protrude from the backside of the substrate.

Claims

1. A method of forming a semiconductor device comprising:

providing conductive material embedded within a first substrate, wherein the first substrate comprises a non-conducting material;

grinding a backside of the first substrate to a thickness wherein at least 1 μ

m of the non-conducting material remains covering the conductive material embedded within the first substrate;

employing chemical mechanical polishing (CMP) with an undiscerning slurry to the backside of the first substrate, thereby exposing the conductive material; and

employing a spin wet-etch, with a protective formulation, to remove a thickness y of the non-conducting material from the backside of the first substrate, thereby causing the conductive material to protrude from the backside of the first substrate.

2. The method of claim 1, wherein the undiscerning slurry comprises an oxidizer and an additive.

3. The method of claim 2, wherein the oxidizer is selected from a group consisting of H₂O₂, KIO₃, ammonium persulfate (APS), KNO₃, and a combination of H₂O₂, KIO₃, ammonium persulfate (APS), or KNO₃.

4. The method of claim 3, wherein the additive comprises a Cu inhibitor, benzotriazole (BTA), ethylenediaminetetraacetic acid (EDTA), or combinations of BTA and EDTA.

5. The method of claim 4, wherein the Cu inhibitor comprises sulfuric acid, hydroxyethylidine, diphosphonic acid, and tolytriazole.

6. The method of claim 1, wherein the protective formulation comprises a B group, and a C group, wherein the B group consists of —

(CH₂)n, wherein n is from 1 to 20, and wherein the C group has an affinity to Cu.

7. The method of claim 6, wherein the protective formulation is an aromatic ring or a heteroaromatic ring.

8. The method of claim 6, wherein the protective formulation further comprises an A group and wherein the A group is halogen, —

H, —

CH₃, —

(CH₂)n, —

SH, —

OH, —

COOH, —

NH2, CN, —

CHO, —

OR, —

NHR or —

SR, wherein R is in an alkyl group.

9. The method of claim 6, wherein the protective formulation further comprises an A group and wherein the A group is halogen, H, CH₃, (CH₂)n, SH, OH, COOH, NH2, CN, CHO, OR, NHR or SR, wherein R is in an aryl group.

10. The method of claim 6 wherein the C group is from an amino group, a nitro group, a mercapto group, or a carboxyl acid group.

11. The method of claim 1 further comprising:

following CMP, etching substrate material from the planarized backside of the first substrate using chemicals in a spinning tool that are selective to non-conducting material and non-selective to conductive material.

12. The method of claim 1, wherein the conductive material forms through substrate vias (TSVs).

13. The method of claim 1 further comprising:

bonding a second substrate to a face side of the first substrate.

14. The method of claim 1, wherein the spin wet-etch employs tetramethyl ammonium hydroxide (TMAH).

15. The method of claim 14, wherein about 2.38% +/−

0.02% TMAH is employed in the spin wet-etch.

16. A method of manufacturing a semiconductor structure, comprising:

providing a substrate with a bulk material containing a plurality of through substrate vias (TSVs), ranging in thickness from T_max to T_min;

mechanically grinding a backside of the substrate, wherein a remaining thickness X of the bulk material continues to protect the plurality of TSVs;

chemical mechanical polishing the backside of the substrate thereby reducing the respective thicknesses of the plurality of TSVs to T_cmp, wherein T_cmp≦

T_min; and

etching a thickness y of the bulk material from the backside of the substrate in a spin wet-etch employing a protective formulation.

17. The method of claim 16, wherein the spin wet-etch employs between about 2.0% and 2.8% of tetramethyl ammonium hydroxide (TMAH).

18. The method of claim 16, wherein a mechanical grinder employed in the mechanically grinding step is controlled by an in situ gauge.

19. The method of claim 18, wherein the in situ gauge is an infra-red laser gauge.

20. A method of manufacturing a semiconductor structure comprising:

providing a silicon wafer with a copper through substrate via (TSV);

backgrinding the silicon wafer, wherein a remaining thickness of silicon continues to protect the TSV;

using a slurry with an oxidizer, planarizing a backside of the silicon wafer; and

wet-etching the silicon wafer in a spinning tool employing an etchant having an etch selectivity ratio between copper and silicon of between about 1;

10 and about 1;

1000.