APPARATUS FOR UV DAMAGE REPAIR OF LOW K FILMS PRIOR TO COPPER BARRIER DEPOSITION

• US 20100267231A1
• Filed: 03/17/2010
• Published: 10/21/2010
• Est. Priority Date: 10/30/2006
• Status: Abandoned Application

• Current Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Original Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Inventors: Benzing, Victoria Shannon, van Schravendijk, Bart
• Application Number:
  US12/726,263
• Publication Number:
  US 20100267231A1
• Time in Patent Office: Days
• US Class Current: 438/653
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/67115 mainly by radiation
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas

Abstract

An apparatus and method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. A semiconductor substrate processing system may be configured to include degas and plasma pre-clean modules, UV process modules, copper diffusion barrier deposition modules and copper seed deposition modules such that the substrate is held under vacuum and is not exposed to ambient air after low k damage repair and before copper barrier layer deposition. Inventive methods provide for treatment of a damaged low-k dielectric on a semiconductor substrate with UV radiation to repair processing induced damage and barrier layer deposition prior breaking vacuum.

Claims

1. A semiconductor substrate processing apparatus, comprising:

a. a load lock;

b. a transport module having a load chamber, a transfer chamber, and a pass-through chamber located between the load chamber and the transfer chamber, the load chamber being coupled to the load lock;

c. a robot configured to transfer a wafer between the load lock and the load chamber;

d. a UV process module coupled at least one of the load chamber and the transfer chamber; and

e. a metal deposition process module coupled to the transfer chamber.

2. The apparatus of claim 1, wherein the apparatus operates under vacuum such that a substrate is not exposed to ambient or other conditions that would damage a low-k dielectric during or between processing in the UV and metal deposition process modules.

3. The apparatus of claim 1, comprising a plurality of UV process modules.

4. The apparatus of claim 1, wherein the deposition process module comprises at least one of a barrier deposition module and a metal seed deposition module.

5. The apparatus of claim 1, wherein each process module is configured to process one wafer at a time.

6. The apparatus of claim 4, wherein the metal seed deposition module is a copper seed deposition module.

7. The apparatus of claim 1, further comprising a pre-clean module.

8. The apparatus of claim 1, wherein the metal deposition process module comprises at least one of a chemical vapor deposition module, an atomic layer deposition module, and a physical vapor deposition module.

9. The apparatus of claim 6, wherein the metal deposition process module further comprises a bulk copper deposition module.

10. The apparatus of claim 1, wherein the UV process module comprises

a. a temperature controlled substrate holder;

and,

b. one or more UV light sources configured to generate UV radiation with a power density of about 500 mW-5 W/cm²;

wherein the UV light has a wavelength from about 150-500 nm.

11. The apparatus of claim 10, wherein the UV process module further comprises a gas inlet and a vacuum outlet.

12. The apparatus of claim 10, wherein the UV light source comprises an array of individual UV sources selected from a group consisting of mercury vapor lamps, xenon lamps, deuterium lamps, excimer lamps, excimer lasers, and combinations thereof.

13. The apparatus of claim 10, wherein the UV process module further comprises a reflector.

14. The apparatus of claim 10, wherein the UV process module further comprises a filter.

19. The method of claim 15, wherein the method is performed in the apparatus of claim 1.

15. A method of forming a semiconductor device in a damascene processing, comprising:

a. receiving in a semiconductor processing apparatus a semiconductor device substrate comprising a carbon-containing low-k dielectric layer having formed therein a feature;

b. exposing the feature to UV radiation in a UV process module of the apparatus; and

c. depositing a barrier layer on the wafer in a process module of the apparatus; and

,

wherein the substrate is not exposed to ambient conditions after exposing to UV radiation and before depositing the barrier layer.

16. The method of claim 15, further comprising depositing a copper seed layer on the substrate in a metal seed deposition process module of the apparatus;

wherein the wafer is not exposed to ambient conditions after exposing to UV radiation and before depositing the seed layer.

17. The method of claim 16, further comprising pre-cleaning the substrate and exposing the substrate to UV radiation after pre-cleaning.

18. The method of claim 17, further comprising degassing the substrate and exposing the wafer to UV radiation during degassing.

20. An apparatus for repairing process-induced damage on a semiconductor device substrate, comprising:

(a) a semiconductor substrate processing apparatus, comprising;

a. a load lock;

b. a transport module having a load chamber, a transfer chamber, and a pass-through chamber located between the load chamber and the transfer chamber, the load chamber being coupled to the load lock;

c. a robot configured to transfer a wafer between the load lock and the load chamber;

d. a UV process module coupled at least one of the load chamber and the transfer chamber; and

e. a metal deposition process module coupled to the transfer chamber; and

(b) a controller comprising program instructions for conducting a method in accordance with claim 15.