METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS

• US 20100267236A1
• Filed: 06/28/2010
• Published: 10/21/2010
• Est. Priority Date: 05/21/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: LIU, Huang, SEE, Alex KH, CONG, Hai, KOH, Hui Peng, YE, Jianhui, HSIA, Liang Choo, LU, Wei, ZHOU, Mei Sheng
• Granted Patent: US 7,960,283 B2
• Time in Patent Office: Days
• US Class Current: 438/682
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

Claims

1. A method for forming a transistor in an integrated circuit (IC) comprising:

providing a substrate having a gate on the substrate, the gate having gate sidewalls, and diffusion regions in the substrate adjacent to the gate;

forming dielectric spacers on the gate sidewalls;

forming metal silicide contacts over the diffusion regions, wherein portions of the metal silicide contacts are covered by the spacers; and

pulling back the dielectric spacers to reduce stress on the metal silicide contacts.