METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING PLANARIZED SPACERS

• US 20100267238A1
• Filed: 04/20/2009
• Published: 10/21/2010
• Est. Priority Date: 04/20/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Johnson, Frank S., Bonser, Douglas
• Granted Patent: US 8,268,727 B2
• Time in Patent Office: Days
• US Class Current: 438/692
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods of fabricating a semiconductor device on and in a semiconductor substrate are provided. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, wherein the sacrificial mandrel has sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having an upper portion and a lower portion. The upper portion of the sidewall spacers is removed. The sacrificial mandrel is removed and the semiconductor substrate is etched using the lower portion of the sidewall spacers as an etch mask.

Claims

1. A method of fabricating a semiconductor device on and in a semiconductor substrate, the method comprising the steps of:

forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls;

forming sidewall spacers adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having an upper portion and a lower portion;

removing the upper portion of the sidewall spacers;

removing the sacrificial mandrel; and

etching the semiconductor substrate using the lower portion of the sidewall spacers as an etch mask.

2. The method of claim 1, wherein the step of removing the upper portion comprises removing the upper portion using a CMP process.

3. The method of claim 1, wherein the step of removing the upper portion comprises removing the upper portion using an etch process.

4. The method of claim 1, wherein the sidewall spacers and the sacrificial mandrel each have a first thickness, further comprising the step of:

depositing a planarizing layer overlying the substrate, the sacrificial mandrel, and the sidewall spacers, the planarizing layer having a second thickness greater than the first thickness; and

etching the planarizing layer back to substantially the first thickness.

5. The method of claim 4, further comprising the step of etching the planarizing layer, the upper portion of the sidewall spacers, and the sacrificial mandrel at substantially the same rate.

6. The method of claim 4, further comprising the step of removing the planarizing layer.

7. The method of claim 4, wherein the step of depositing a planarizing layer comprises depositing a silicon-comprising planarizing layer.

8. The method of claim 4, wherein the step of forming a sacrificial mandrel comprises:

forming a first mandrel layer overlying the substrate;

forming a second mandrel layer overlying the first mandrel layer, wherein the first and second mandrel layers have different compositions; and

etching the first and second mandrel layers to form the sacrificial mandrel.

9. The method of claim 8, wherein the step of forming sidewall spacers and the step of forming a second mandrel layer comprise forming sidewall spacers and forming a second mandrel layer having the same composition.

10. The method of claim 8, further comprising the step of etching the planarizing layer, the upper portion of the sidewall spacers, and the second mandrel layer at substantially the same rate.

11. The method of claim 10, wherein the step of etching the planarizing layer, the upper portion of the sidewall spacers, and the second mandrel layer further comprises etching the planarizing layer, the upper portion of the sidewall spacers, and the second mandrel layer selectively from the first mandrel layer.

12. A method of fabricating a semiconductor device on and in a semiconductor substrate, the method comprising the steps of:

forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls;

forming sidewall spacers adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having an upper portion and a lower portion;

reducing the aspect ratio of the sidewall spacers with a chemical mechanical planarization process that removes the upper portion;

removing the sacrificial mandrel; and

etching the semiconductor substrate using the lower portion of the sidewall spacers as an etch mask.

13. The method of claim 12, wherein the step of forming a sacrificial mandrel comprises:

forming a first mandrel layer overlying the substrate;

forming a second mandrel layer overlying the first mandrel layer, wherein the first and second mandrel layers have different compositions; and

etching the first and second mandrel layers to form the sacrificial mandrel.

14. The method of claim 13, wherein the step of reducing comprises the step of removing the second mandrel layer selectively from the first mandrel layer.

15. The method of claim 13, wherein the step of forming sidewall spacers and the step of forming a second mandrel layer comprise forming sidewall spacers and forming a second mandrel layer having the same composition.

16. A method of fabricating a semiconductor device on and in a semiconductor substrate, the substrate having a surface, the method comprising the steps of:

forming a sacrificial mandrel overlying the surface of the substrate, the sacrificial mandrel having sidewalls;

forming sidewall spacers adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having an upper portion and a lower portion;

depositing a planarizing layer overlying the surface of the substrate, the sacrificial mandrel, and the sidewall spacers;

etching the sacrificial mandrel, the sidewall spacers, and the planarizing layer at substantially the same rate until the upper portion of the sidewall spacers is removed;

removing the planarizing layer;

removing the sacrificial mandrel; and

etching the semiconductor substrate using the lower portion of the sidewall spacers as an etch mask.

17. The method of claim 16, wherein the step of depositing a planarizing layer comprises depositing a silicon-comprising planarizing layer.

18. The method of claim 16, wherein the step of forming a sacrificial mandrel comprises:

forming a first mandrel layer overlying the substrate;

forming a second mandrel layer overlying the first mandrel layer, wherein the first and second mandrel layers have different compositions; and

etching the first and second mandrel layers to form the sacrificial mandrel.

19. The method of claim 18, wherein the step of etching the sacrificial mandrel comprises etching the sacrificial mandrel until the upper portion is removed and such that the second mandrel layer is selectively removed from the first mandrel layer.

20. The method of claim 18, wherein the step of forming sidewall spacers and the step of forming a second mandrel layer comprise forming sidewall spacers and forming a second mandrel layer having the same composition.