DATA STORAGE SYSTEM COMPRISING MEMORY CONTROLLER AND NONVOLATILE MEMORY

• US 20100268872A1
• Filed: 04/19/2010
• Published: 10/21/2010
• Est. Priority Date: 04/20/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Dong Jin, KIM, Taek-Sung, HWANG, Seong Sik, KWON, Hyuck-Sun, KIM, Kwang Ho
• Application Number:
  US12/762,625
• Publication Number:
  US 20100268872A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A data storage system comprising a storage device comprising at least one nonvolatile memory, and a controller connected to the storage device through a channel. The memory controller sends part or all of a command, address and data for a next operation to the nonvolatile memory while the nonvolatile memory device is in a busy state. The memory controller then performs a background operation while the nonvolatile memory device remains in the busy state.

Claims

1. A data storage system, comprising:

a storage device comprising a plurality of nonvolatile memories each capable of assuming a busy state and a ready state; and

a controller interfacing with the storage device via a channel and configured to transmit a part or all of a command, address and data for an operation to a selected nonvolatile memory in the storage device while the selected nonvolatile memory is in the busy state;

wherein the storage device stores the transmitted part or all of the command, address and data and the controller performs a background operation while the selected nonvolatile memory remains in the busy state.

2. The data storage system of claim 1, wherein the command is one of a program command, an erase command, and a read command.

3. The data storage system of claim 1, wherein the background operation comprises one of garbage collection, a merge operation, and a map data update or backup operation.

4. The data storage system of claim 1, wherein each of the nonvolatile memories is configured to latch the part or all of the command, the address and data transmitted from the controller.

5. The data storage system of claim 4, wherein each of the nonvolatile memories comprises:

a ready/busy control unit configured to generate a ready/busy control signal;

a command and address register block configured to latch an address and a command received from the controller and to operate in response to the ready/busy control signal; and

a program/read/erase control unit configured to control an operation based on the command and address latched in the command and address register block in response to the ready/busy control signal.

6. The data storage system of claim 5, wherein the command and address register block is configured to latch a command and an address received from the controller during a ready state or a busy state of the ready/busy control signal;

and

wherein the address and command received from the controller during the busy state are respectively sent to a row decoder and the program/read/erase control unit after the ready/busy control signal changes to the ready state.

7. The data storage system of claim 5, wherein each of the nonvolatile memories further comprises a page buffer block that operates under control of the program/read/erase control unit and is configured to read data from a memory cell array and to program data to the memory cell array.

8. The data storage system of claim 7, wherein the page buffer block comprises:

a switch configured to operate under control of the program/read/erase control unit;

a page register configured to store data received through the switch during a ready state of a corresponding nonvolatile memory; and

a buffer register configured to store data received through the switch during a busy state of the corresponding nonvolatile memory.

9. The data storage system of claim 8, wherein where the corresponding nonvolatile memory is set to the busy state, the program/read/erase control unit controls the switch to send data stored in the buffer register to the page register.

10. The data storage system of claim 1, wherein the data storage system is one of a solid state disk and a memory card.

11. The data storage system of claim 1, wherein the busy state is one of a programming busy state, a read busy state and an erase busy state.

12. The data storage system of claim 1, wherein at least one of the nonvolatile memories comprises a flash memory.