INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS

• US 20100268895A1
• Filed: 04/15/2009
• Published: 10/21/2010
• Est. Priority Date: 04/15/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William John, Ghai, Sanjeev, Guthrie, Guy Lynn, Powell, Stephen
• Granted Patent: US 10,489,293 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

Claims

1. A method comprising:

requesting, by a processor element, access to a cache memory to conduct operations in the cache memory, the operations including load operations and store operations;

interrupting, by control logic, a store operation in progress in the cache memory when the processor element sends a load operation to the cache memory;

performing, by the cache memory, the load operation; and

scheduling, by the control logic, the store operation for access to the cache memory to conduct a remainder of the store operation after the load operation completes.

2. The method of claim 1, further comprising arbitrating, by an arbitration mechanism, to determine an order in which the cache memory performs load and store operations.

3. The method of claim 1, wherein the cache memory is an L2 cache memory.

4. The method of claim 1, wherein the processor element is a processor core that includes an L1 cache memory.

5. The method of claim 3, wherein the L2 cache memory is a store-in cache memory.

6. A method comprising:

sending, by a processor element, a plurality of requests for memory operations to a cache memory, the memory operations including load operations and store operations;

receiving, by control logic for the cache memory, a request for a first load operation;

performing, by the cache memory, the first load operation that the request for a first load operation specifies;

receiving, by the control logic for the cache memory, a request for a first store operation;

commencing, by the cache memory, performance of the first store operation that the request for first store operation specifies such that the first store operation is in progress;

receiving, by the cache memory, a request for a second load operation while the first store operation is in progress in the cache memory; and

interrupting, by the control logic, the in progress first store operation to perform the second load operation.

7. The method of claim 6, further comprising delaying, by the control logic, performance of a remaining portion of the first store operation until performance of the second load operation completes.

8. The method of claim 6, further comprising arbitrating, by an arbitration mechanism, to determine an order in which the cache memory performs the load and store operations.

9. The method of claim 6, wherein the cache memory is an L2 cache memory.

10. The method of claim 6, wherein the processor element is a processor core that includes an L1 cache memory.

11. A cache memory system comprising:

a processor element;

a cache memory, coupled to the processor element, that receives a request from the processor element to conduct operations in the cache memory, the operations including load operations and store operations;

the cache memory including control logic that interrupts a store operation in progress in the cache memory when the processor element sends a load operation to the cache memory, such that the cache memory performs the load operation instead of a remainder of the store operation, wherein the control logic schedules the remainder of the store operation for completion by the cache memory after the load operation completes.

12. The cache memory system of claim 11, further comprising an arbitration mechanism that arbitrates to determine an order in which the cache memory performs load and store operations.

13. The cache memory system of claim 11, wherein the cache memory is an L2 cache memory.

14. The cache memory system of claim 11, wherein the processor element is a processor core that includes an L1 cache memory.

15. The cache memory system of claim 13, wherein the L2 cache memory is a store-in cache memory

16. A information handling system (IHS), comprising:

a processor element;

a cache memory, coupled to the processor element, that receives a request from the processor element to conduct operations in the cache memory, the operations including load operations and store operations;

the cache memory including control logic that interrupts a store operation in progress in the cache memory when the processor element sends a load operation to the cache memory, such that the cache memory performs the load operation instead of a remainder of the store operation, wherein the control logic schedules the remainder of the store operation for completion by the cache memory after the load operation completes; and

a system memory coupled to the cache memory.

17. The information handling system (IHS) of claim 16, further comprising an arbitration mechanism that arbitrates to determine an order in which the cache memory performs load and store operations.

18. The information handling system (IHS) of claim 16, wherein the cache memory is an L2 cache memory.

19. The information handling system (IHS) of claim 16, wherein the processor element is a processor core that includes an L1 cache memory.

20. The information handling system (IHS) of claim 18, wherein the L2 cache memory is a store-in cache memory.