MEMORY DEVICE AND MEMORY DEVICE CONTROLLER

• US 20100268897A1
• Filed: 04/15/2010
• Published: 10/21/2010
• Est. Priority Date: 04/16/2009
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Otsuka, Takeshi, OKAMOTO, Keishi, Yamashita, Hideaki
• Application Number:
  US12/760,842
• Publication Number:
  US 20100268897A1
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A memory device controller interposed between a memory device and a host device includes a data communication unit configured to transfer data to and from the memory device in synchronization with a clock signal. The data communication unit supports a single edge synchronization mode in which data is transferred in synchronization with either one of a rising edge and a falling edge of the clock signal, and a double edge synchronization mode in which data is transferred in synchronization with both the rising edge and the falling edge. The data communication unit transfers data in the double edge synchronization mode when data is transferred by the memory device operating as a bus master.

Claims

1. A memory device connectable to a host device via a memory device controller, comprising:

a memory module for storing data; and

a data communication unit configured to communicate data with the memory device controller in synchronization with a predetermined clock signal, in order to write or read data to or from the memory module,

wherein the data communication unit is capable of transferring data in a single edge synchronization mode in which data is transferred in synchronization with either one of a rising edge and a falling edge of the clock signal or in a double edge synchronization mode in which data is transferred in synchronization with both the rising edge and the falling edge,

the memory device can be set to operate as a bus master, and

when the memory device is set to operate as a bus master, the data communication unit transfers data in the double edge synchronization mode.

2. The memory device according to claim 1, further comprising a buffer memory for temporarily storing data to be read from the memory module or data to be written in the memory module,

wherein when data is transferred with the memory device operating as a bus master, the data communication unit switches between the single edge synchronization mode and the double edge synchronization mode, according to state of stored data in the buffer memory.

3. The memory device according to claim 2, further comprising a determination unit configured to determine a free space of the buffer memory,

wherein when data is transferred to the memory device operating as a bus master from the memory device controller, based on the result of determination by the determination unit, the data communication unit transfers data in the double edge synchronization mode when the free space of the buffer memory is equal to or more than a predetermined value, and transfers data in the single edge synchronization mode when the free space of the buffer memory is less than the predetermined value.

4. The memory device according to claim 2, further comprising a determination unit configured to determine amount of data stored in the buffer memory,

wherein when data is transferred from the memory device operating as a bus master to the memory device controller, based on the result of determination by the determination unit, the data communication unit transfers data in the double edge synchronization mode when the amount of data stored in the buffer memory is equal to or more than a predetermined value, and transfers data in the single edge synchronization mode when the amount of data stored in the buffer memory is less than the predetermined value.

5. A memory device controller interposed between a memory device and a host device and connectable to the memory device through a predetermined interface, the memory device controller comprising a data communication unit configured to transfer data to and from the memory device in synchronization with a clock signal,

wherein the data communication unit supports a single edge synchronization mode in which data is transferred in synchronization with either one of a rising edge and a falling edge of the clock signal, and a double edge synchronization mode in which data is transferred in synchronization with both the rising edge and the falling edge, and

the data communication unit transfers data in the double edge synchronization mode when data is transferred by the memory device operating as a bus master.

6. The memory device controller according to claim 5, further comprising a device information requesting unit configured to request device information from the memory device when connection of the memory device to the memory device controller is detected,

wherein the data communication unit switches between transfer in the double edge synchronization mode and transfer in the single edge synchronization mode based on the device information acquired from the memory device, to transfer data.

7. The memory device controller according to claim 6, which determines whether or not the memory device supports the double edge synchronization mode based on the device information received from the memory device, and transmits, to the memory device, a command for commanding the memory device to operate as a bus master and transfer data in the double edge synchronization mode, when the memory device supports the double edge synchronization mode.

8. The memory device controller according to claim 6, which determines an interface specification which is supported by the memory device based on the device information received from the memory device, and changes an interface specification of the memory device to the interface specification determined to be supported by the memory device.

9. The memory device controller according to claim 6, wherein the device information includes information about speed of at least one of writing and reading data to and from the memory device.

10. The memory device controller according to claim 6, wherein the device information includes information about current consumptions for writing and reading data in the double edge synchronization mode and information about current consumptions for writing and reading data in the single edge synchronization mode.