MULTI-NODE CONFIGURATION OF PROCESSOR CARDS CONNECTED VIA PROCESSOR FABRICS

• US 20100268986A1
• Filed: 07/02/2010
• Published: 10/21/2010
• Est. Priority Date: 06/14/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Verdoorn, William Garrett JR., Walls, Andrew Dale
• Granted Patent: US 8,095,691 B2
• Time in Patent Office: Days
• US Class Current: 714/10
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

Claims

1-7. -7. (canceled)

9. A system, comprising:

a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics;

a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and

a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes; and

node management code executed by at least one processor card in each of the first and second nodes to perform operations, the operations comprising;

detecting a failure of one processor card in one of the first or second node;

performing a failover to use the first or second node that does not include the failed processor card.

8. The system of claim 9, further comprising:

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor to operate without the failed processor in response to the determining that the node includes at least one operational processor card; and

wherein the performing of the failover to use the first or second node not including the failed processor card is performed in response to the determining that the node does not include at least one operational processor card.

10-14. -14. (canceled)

16. A system, comprising:

a first midplane including;

a first and second processor cards, wherein each processor card includes a processor fabric; and

a first communication interface connecting the first and second processor cards to enable communication between the first and second processor cards; and

a second midplane including;

a third and fourth processor cards, wherein each processor card includes a processor fabric, wherein the first and third processor cards connect via their processor fabrics and wherein the second and fourth processor cards connect via their processor fabrics; and

a second communication interface connecting the third and fourth processor cards to enable communication between the third and fourth processor cards;

management code executed by at least one processor card to perform operations, the operations comprising;

detecting a failure of one processor card; and

performing a failover to use processor cards connected via their processor fabrics that are not connected via processor fabrics to the failed processor card.

15. The system of claim 16, wherein the management code is executed to perform further operations comprising:

determining whether the failed processor card is connected via the processor fabrics to an operational processor card;

reconfiguring the failed and operational cards connected via their processor fabrics to operate without the failed processor in response to the determining that the failed processor card is connected via the processor fabrics to the operational processor card; and

wherein the performing of the failover to use the processor cards connected via their processor fabrics that are not connected via processor fabrics to the failed processor card is performed in response to the determining that the failed processor card is not connected via the processor fabrics to the operational processor card.

17-19. -19. (canceled)

21. A method, comprising:

configuring a first node comprising a plurality of processor cards, each having a processor fabric connected via their processor fabrics;

configuring a second node comprising a plurality of processor cards, each having a processor fabric, connected via their processor fabrics;

configuring a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes;

detecting a failure of one processor card in one of the first or second node; and

performing a failover to use the first or second node that does not include the failed processor card.

20. The method of claim 21, further comprising:

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor to operate without the failed processor in response to the determining that the node includes at least one operational processor card; and

wherein the performing of the failover to use the first or second node not including the failed processor card is performed in response to the determining that the node does not include at least one operational processor card.

22-24. -24. (canceled)

26. An article of manufacture comprising code implemented in processor cards each having a processor fabric and coupled to one of a plurality of communication interfaces, wherein the code causes operations to be performed, the operations comprise:

configuring a first node comprising a plurality of the processor cards connected via their processor fabrics;

configuring a second node comprising a plurality of the processor cards connected via their processor fabrics;

configuring the communication interfaces, wherein each communication interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes;

detecting a failure of one processor card in one of the first or second node; and

performing a failover to use the first or second node that does not include the failed processor card.

25. The article of manufacture of claim 26, wherein the operations further comprise:

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor to operate without the failed processor in response to the determining that the node includes at least one operational processor card; and

wherein the performing of the failover to use the first or second node not including the failed processor card is performed in response to the determining that the node does not include at least one operational processor card.