Managing Threads in a Wake-and-Go Engine

• US 20100269115A1
• Filed: 04/16/2009
• Published: 10/21/2010
• Est. Priority Date: 04/16/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Swanberg, Randal C, Arimilli, Ravi K., Sharma, Satya P.
• Granted Patent: US 8,230,201 B2
• Time in Patent Office: Days
• US Class Current: 718/103
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism detects a thread running on a first processing unit within a plurality of processing units that is waiting for an event that modifies a data value associated with a target address. The wake-and-go mechanism creates a wake-and-go instance for the thread by populating a wake-and-go storage array with the target address. The operating system places the thread in a sleep state. Responsive to detecting the event that modifies the data value associated with the target address, the wake-and-go mechanism assigns the wake-and-go instance to a second processing unit within the plurality of processing units. The operating system on the second processing unit places the thread in a non-sleep state.

Claims

1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:

detecting a thread running on a first processing unit within a plurality of processing units that is waiting for an event that modifies a data value associated with a target address;

creating a wake-and-go instance for the thread by populating a wake-and-go storage array with the target address;

placing the thread in a sleep state;

responsive to detecting the event that modifies the data value associated with the target address, assigning the wake-and-go instance to a second processing unit within the plurality of processing units; and

placing the thread in a non-sleep state on the second processing unit.

2. The method of claim 1, wherein assigning the wake-and-go instance to the second processing unit comprises:

determining that the second processing unit has a lowest processor utilization within the plurality of processing units.

3. The method of claim 1, wherein assigning the wake-and-go instance to the second processing unit comprises:

determining that the second processing unit has a lowest priority thread running within the plurality of processing units.

4. The method of claim 3, wherein placing the thread in a non-sleep state on the second processing unit comprises placing the lowest priority thread in a sleep state on the second processing unit.

5. The method of claim 1, wherein the wake-and-go storage array is a first wake-and-go storage array associated with the first processing unit and wherein assigning the wake-and-go instance to the second processing unit comprises transferring the wake-and-go instance from the first wake-and-go storage array to a second wake-and-go storage array associated with the second processing unit.

6. The method of claim 1, wherein the wake-and-go storage array is a central repository wake-and-go storage array.

7. The method of claim 1, wherein the wake-and-go storage array is a content addressable memory and an address on a bus is used to address the content addressable memory.

8. The method of claim 7, wherein responsive to detecting the event that modifies the data value associated with the target address, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

9. The method of claim 1, wherein the first processing element and the second processing element are processing cores in a multiple core processor.

10. The method of claim 1, wherein the event is an asynchronous event caused by a device outside a processor running the thread.

11. The method of claim 1, wherein the method is performed by a wake-and-go mechanism.

12. The method of claim 11, wherein the wake-and-go mechanism is one of a hardware component within a processor, a hardware component associated with the wake-and-go storage array, or a hardware component associated with a system bus.

13. A data processing system, comprising:

a wake-and-go mechanism; and

a wake-and-go storage array,

wherein the wake-and-go mechanism is configured to;

detect a thread running on a first processing unit within a plurality of processing units that is waiting for an event that modifies a data value associated with a target address;

create a wake-and-go instance for the thread by populating a wake-and-go storage array with the target address;

place the thread in a sleep state;

responsive to detecting the event that modifies the data value associated with the target address, assign the wake-and-go instance to a second processing unit within the plurality of processing units; and

place the thread in a non-sleep state on the second processing unit.

14. The data processing system of claim 13, wherein assigning the wake-and-go instance to the second processing unit comprises:

determining that the second processing unit has a lowest processor utilization within the plurality of processing units.

15. The data processing system of claim 13, wherein assigning the wake-and-go instance to the second processing unit comprises:

determining that the second processing unit has a lowest priority thread running within the plurality of processing units.

16. The data processing system of claim 15, wherein placing the thread in a non-sleep state on the second processing unit comprises placing the lowest priority thread in a sleep state on the second processing unit.

17. The data processing system of claim 13, wherein the wake-and-go storage array is a first wake-and-go storage array associated with the first processing unit and wherein assigning the wake-and-go instance to the second processing unit comprises transferring the wake-and-go instance from the first wake-and-go storage array to a second wake-and-go storage array associated with the second processing unit.

18. The data processing system of claim 13, wherein the wake-and-go storage array is a central repository wake-and-go storage array.

19. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

detect a thread running on a first processing unit within a plurality of processing units that is waiting for an event that modifies a data value associated with a target address;

create a wake-and-go instance for the thread by populating a wake-and-go storage array with the target address;

place the thread in a sleep state;

responsive to detecting the event that modifies the data value associated with the target address, assign the wake-and-go instance to a second processing unit within the plurality of processing units; and

place the thread in a non-sleep state on the second processing unit.

20. The computer program product of claim 19, wherein wake-and-go storage array is a central repository wake-and-go storage array.