Method for manufacturing semiconductor device, and semiconductor device

• US 20100270613A1
• Filed: 04/20/2010
• Published: 10/28/2010
• Est. Priority Date: 04/23/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Takehara, Kei
• Granted Patent: US 8,071,445 B2
• Time in Patent Office: Days
• US Class Current: 257/332
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source interconnect layer is connected to a source electrode formed in the transistor region immediately above the trench. A gate extending region is provided outside the source extending region, and the gate electrode and a gate interconnect layer are connected. The gate electrode is formed by performing etchback without forming a resist pattern, after a polysilicon film is formed. Here, the polysilicon film remains like a side-wall on the sidewall of the portion of the source interconnect layer protruding from the upper end of the trench.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a second-conductivity-type semiconductor layer on a first-conductivity-type semiconductor layer to be a drain region;

forming first through third trenches that penetrate through said second-conductivity-type semiconductor layer, and are linked to one another;

filling said first through third trenches with a source interconnect layer, and causing said source interconnect layer to protrude from an upper end of said second trench;

filling said first and third trenches with a gate electrode;

bringing a source electrode into contact with said source interconnect layer protruding from the upper end of said second trench; and

bringing a gate interconnect layer into contact with said gate electrode in said third trench.

2. The method according to claim 1, wherein said filling said first and third trenches with said gate electrode includes:

forming a conductive film in said first and third trenches and on said second-conductivity-type semiconductor layer, said conductive film being to be said gate electrode; and

performing etchback on said conductive film, to form a sidewall formed with said conductive film on a sidewall of said source interconnect layer protruding from the upper end of said second trench.

3. The method according to claim 1, wherein said source interconnect layer and said gate electrode are formed with polysilicon film.

4. The method according to claim 1, wherein

said first-conductivity-type semiconductor layer includes:

a cell region in which a MOS transistor structure is provided; and

a terminal region that is adjacent to said cell region, and

said forming said first through third trenches includes forming said first and second trenches in said cell region.

5. A semiconductor device comprising:

a first-conductivity-type semiconductor layer that is to be a drain region;

a second-conductivity-type semiconductor layer formed on said first-conductivity-type semiconductor layer;

first through third trenches penetrating through said second-conductivity-type semiconductor layer, and linked to one another;

a source interconnect layer buried in said first through third trenches, and protruding from an upper end of said second trench;

a gate electrode buried in each of said first and third trenches, and formed on said source interconnect layer;

a source electrode contacting to said source interconnect layer protruding from the upper end of said second trench; and

a gate interconnect layer contacting to said gate electrode in said third trench.

6. The semiconductor device according to claim 5, further comprising:

a side-wall-like conductive film formed on a sidewall of said source interconnect layer protruding from the upper end of said second trench, said side-wall-like conductive film being made of the same material as said gate electrode.