METHOD FOR PROTECTING A GATE STRUCTURE DURING CONTACT FORMATION

• US 20100270627A1
• Filed: 04/22/2009
• Published: 10/28/2010
• Est. Priority Date: 04/22/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hong-Dyi, Su, Pei-Chao, Thei, Kong-Beng, Tao, Hun-Jan, Chuang, Harry Hak-Lay
• Granted Patent: US 8,202,776 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

providing a substrate;

forming at least one gate structure over the substrate;

forming a plurality of doped regions in the substrate;

forming an etch stop layer over the substrate;

removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions;

forming a hard mask layer over the substrate;

removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and

forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.

2. The method of claim 1 wherein forming the hard mask layer over the substrate comprises depositing a material selected from the group consisting of silicon nitride, silicon oxynitride, amorphous carbon material, silicon carbide and combination thereof.

3. The method of claim 1 wherein forming the etch stop layer over substrate comprises depositing a material selected from the group consisting of silicon nitride, silicon oxynitride, amorphous carbon material, silicon carbide and combination thereof.

4. The method of claim 1 further comprising:

forming a first interlevel dielectric (ILD) layer over the etch stop layer;

performing a chemical mechanical polishing process to expose the at least one gate structure;

replacing a dummy gate of the at least one gate structure with a metal gate; and

forming a second ILD layer over the first ILD layer.

5. The method of claim 4 wherein forming the first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions comprises:

performing a first etching process and a second etching process to form contact openings; and

depositing a conductive material in the contact openings.

6. The method of claim 5 wherein performing the first etching process comprises etching the first ILD layer and the second ILD layer until the second portion of the hard mask layer and the second portion of the etch stop layer are reached.

7. The method of claim 5 wherein the first etching process comprises an etching selectivity between the etch stop layer/the hard mask layer and the ILD layers.

8. The method of claim 5 wherein performing the second etching process comprises:

etching through the second portion of the etch stop layer until a silicide feature of the plurality of doped regions is exposed; and

etching through the second portion of the hard mask layer until the metal gate is exposed.

9. A method for fabricating a semiconductor device, the method comprising:

providing a substrate;

forming at least one gate structure over the substrate, wherein the at least one gate structure comprises a dummy gate;

forming an etch stop layer over the substrate, including over the at least one gate structure;

forming a first interlevel dielectric (ILD) layer over the etch stop layer;

performing a chemical mechanical polishing (CMP) process on the first ILD and etch stop layer until a top portion of the at least one gate structure is exposed;

replacing the dummy gate of the at least one gate structure;

forming a hard mask layer over the top portion of the at least one gate structure;

forming a second ILD layer over the first ILD layer, including over the hard mask layer; and

forming one or more contact openings to the at least one gate structure and to the substrate.

10. The method of claim 9 wherein replacing the dummy gate layer of each of the gate structures comprises:

replacing the dummy gate in at least one gate structure over the substrate with a first gate layer, the first gate layer comprising a first material having a first-type work function; and

replacing the dummy gate in at least one gate structure over the substrate with a second gate layer, the second gate layer comprising a second material having a second-type work function.

11. The method of claim 10 wherein forming the hard mask layer over the top portion of the at least one gate structures comprises forming the hard mask layer over at least the first gate layer and the second gate layer of the gate structures.

12. The method of claim 9 wherein forming the hard mask layer over the top portion of the at least one gate structure comprises:

forming a photoresist layer over the hard mask layer;

patterning the photoresist layer to form unprotected portions of the hard mask layer and protected portions of the hard mask layer, wherein the protected portions of the hard mask layer overlie the top portion of the gate structure; and

removing the photoresist layer and the unprotected portions of the hard mask layer.

13. The method of claim 9 wherein forming one or more contact openings to the gate structure and the substrate comprises:

removing portions of the first and second ILD layers to form one or more first contact openings, wherein the one or more first contact openings expose a portion of the etch stop layer and a portion of the hard mask layer;

removing the exposed portions of the etch stop layer and the hard mask layer to form one or more second contact openings, wherein the one or more second contact openings expose a top portion of the substrate and the top portion of the gate structure; and

forming a conductive layer in the first and second contact openings to form contacts to the substrate and the gate structure.

14. The method of claim 13 wherein the first and second ILD layers comprise an oxide material, and wherein the etch stop layer and hard mask layer comprise a silicon nitride material;

and

wherein removing the portions of the first and second ILD layers to form the first contact openings comprises utilizing an etching process having an etching selectivity between the oxide material and the silicon nitride material.

15. The method of claim 9 wherein the etch stop layer and the hard mask layer comprise substantially a same thickness.

16. A semiconductor device comprising:

a substrate having at least one gate structure disposed thereover and a plurality of doped regions disposed therein;

a hard mask layer disposed over the at least one gate structure;

an etch stop layer disposed over the plurality of doped regions;

a dielectric layer disposed over the hard mask layer and etch stop layer; and

one or more contacts, wherein at least one contact extends through the dielectric layer and the hard mask layer to the at least one gate structure, and wherein at least one contact extends through the dielectric layer and the etch stop layer to the plurality of doped regions.

17. The semiconductor device of claim 16 wherein the at least one gate structure comprises a high-k gate dielectric and a metal gate electrode.

18. The semiconductor device of claim 17 wherein the at least one contact extending through the dielectric layer and the hard mask layer is coupled to the metal gate electrode.

19. The semiconductor device of claim 16 wherein the hard mask layer and the etch stop layer comprise substantially a same type of material.

20. The semiconductor device of claim 16 wherein the hard mask layer and the etch stop layer comprise substantially a same thickness.