I/O Buffer with Low Voltage Semiconductor Devices

• US 20100271118A1
• Filed: 04/23/2009
• Published: 10/28/2010
• Est. Priority Date: 04/23/2009
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Kriz, John, Bhattacharya, Dipankar, Kumar, Pankaj, Kothandaraman, Makeshwar, Smooha, Yehuda, Nagy, Jeffrey
• Granted Patent: US 7,936,209 B2
• Time in Patent Office: Days
• US Class Current: 327/543
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

Claims

1. A method for protection from an over-voltage condition in an input/output (“

I/O”

) buffer having first and second I/O transistors, wherein the first I/O transistor is coupled to a first over-voltage protection circuit, and the second I/O transistor is coupled to a second over-voltage protection circuit, comprising;

a) generating first and second bias voltages from an operating voltage of the buffer;

b) generating a third bias voltage from either i) the first bias voltage, or ii) an output signal voltage of the buffer;

c) generating a fourth bias voltage from either i) the second bias voltage, or ii) the output signal voltage of the buffer;

d) providing the third and fourth bias voltages to the first and second over-voltage protection circuits, respectively;

e) preventing, by the first over-voltage protection circuit, the over-voltage condition on at least the first I/O transistor, wherein the first I/O transistor comprises a P-channel FET, and the first over-voltage protection circuit comprises a first over-voltage transistor and a second over-voltage protection transistor, wherein the first and second over-voltage protection transistors comprise P-channel field effect transistors (FETs), and

f) preventing, by the second over-voltage protection circuit, the over-voltage condition on at least the second I/O transistor, wherein the second I/O transistor comprises an N-channel FET, and the second over-voltage protection circuit comprises (i) a third over-voltage protection transistor and (ii) a fourth over-voltage protection transistor wherein the third and fourth over-voltage protection transistors comprise N-channel FETs,

wherein the over-voltage condition comprises at least one of a DC and a transient over-voltage condition, and wherein the FETs are fabricated with a gate oxide thickness of substantially 26 Angstroms.

3. The method as recited in claim 1, wherein, the first bias voltage and the second bias voltage are the same signal.

2. (canceled)

4. An apparatus for protection from an over-voltage condition in an input/output (“

I/O”

) buffer having first and second I/O transistors, wherein the first I/O transistor is coupled to a first over-voltage protection circuit, and the second I/O transistor is couple to a second over-voltage protection circuit, comprising;

a) a first bias voltage and a second bias voltage;

b) a first dynamic bias circuit to generate a third bias voltage from either i) the first bias voltage, or ii) an output signal voltage of the buffer, wherein the first dynamic bias circuit comprises a first and a second N-channel field effect transistor (FET);

c) a second dynamic bias circuit to generate a fourth bias voltage from either i) the second bias voltage, or ii) an output signal voltage of the buffer, wherein the second dynamic bias circuit comprises a first and a second P-channel FET;

d) a first over-voltage protection circuit driven by the third bias voltage, wherein the first over-voltage protection circuit is adapted to prevent DC and transient over-voltage conditions on the first I/O transistor and wherein the first over-voltage protection circuit comprises (i) a first over-voltage protection transistor and (ii) a second over-voltage protection transistor, wherein the first and second over-voltage protection comprise P-channel FETs; and

e) a second over-voltage protection circuit driven by the fourth bias voltage, wherein the second over-voltage protection circuit is adapted to prevent DC and transient over-voltage conditions on the second I/O transistor and wherein the second over-voltage protection circuit comprises (i) a third over-voltage protection transistor and (ii) a fourth over-voltage protection transistor, wherein the third and fourth over-voltage protection transistors comprise N-channel FETs;

wherein the first I/O transistor comprises a P-channel FET and the second I/O transistor comprises an N-channel FET, and wherein the FETs are fabricated with a gate oxide thickness of substantially 26 Angstroms.

5. The apparatus as recited in claim 4, wherein the first I/O transistor is configured to pull-up the output signal voltage of the buffer, and the second I/O transistor is configured to pull-down the output signal voltage of the buffer.

7. The apparatus as recited in claim 4, wherein the first over-voltage protection transistor is driven by the first bias voltage, and the second over-voltage transistor is driven by the third bias voltage, and wherein the third over-voltage protection transistor is driven by the second bias voltage and the fourth over-voltage transistor is driven by the fourth bias voltage.

10. The apparatus as recited in claim 4, wherein when the output signal voltage of the buffer is high, the first dynamic bias circuit sets the third bias voltage to the lower of either i) the first bias voltage or ii) the output signal voltage of the buffer, and the second dynamic bias circuit sets the fourth bias voltage to the higher of either i) the second bias voltage or ii) the output signal voltage of the buffer.

11. The apparatus as recited in claim 4, wherein the first bias voltage and the second bias voltage are generated from an operating voltage of the I/O buffer.

12. The apparatus as recited in claim 11, wherein the first bias voltage and the second bias voltage are each a fixed ratio of the operating voltage of the I/O buffer.

13. The apparatus as recited in claim 11, wherein the operating voltage of the I/O buffer is 3.3V with a +/−

10% tolerance.

14. The apparatus as recited in claim 11, wherein the first bias voltage and the second bias voltage are the same signal.

15. The apparatus as recited in claim 4, wherein the apparatus is implemented in an integrated circuit.

6. (canceled)

8. (canceled)

9. (canceled)

16. An apparatus for protection from an over-voltage condition in an input/output (“

I/O”

) buffer having first and second I/O transistors, wherein the first I/O transistor is coupled to a first over-voltage protection circuit, and the second I/O transistor is couple to a second over-voltage protection circuit, comprising;

a) a first bias voltage;

b) a first dynamic bias circuit configured to generate a second bias voltage from either i) the first bias voltage, or ii) an output signal voltage of the buffer, wherein the first dynamic bias circuit comprises a first and a second N-channel field effect transistor (FET);

c) a second dynamic bias circuit configured to generate a third bias voltage from either i) the first bias voltage, or ii) the output signal voltage of the buffer, wherein the second dynamic bias circuit comprises a first and a second P-channel FET;

d) a first over-voltage protection circuit further comprising a first over-voltage protection transistor driven by the first bias voltage and a second over-voltage protection transistor driven by the second bias voltage, wherein the first over-voltage protection circuit is adapted to prevent DC and transient over-voltage conditions on the first I/O transistor, wherein the first and second over-voltage protection transistors comprise P-channel FETs; and

e) a second over-voltage protection circuit further comprising a third over-voltage protection transistor driven by the first bias voltage and a fourth over-voltage protection transistor driven by the third bias voltage, wherein the second over-voltage protection circuit is adapted to prevent DC and transient over-voltage conditions on the second I/O transistor, wherein the third and fourth over-voltage protection transistors comprise N-channel FETs,

wherein the first I/O transistor comprises a P-channel FET and the second I/O transistor comprises an N-channel FET, and wherein the FETs are fabricated with a gate oxide thickness of substantially 26 Angstroms.

18. The apparatus as recited in claim 16, wherein the first dynamic bias circuit is configured to set the third bias voltage to the lower of either i) the first bias voltage or ii) the output signal voltage of the buffer, and the second dynamic bias circuit is configured to set the fourth bias voltage to the higher of either i) the second bias voltage or ii) the output signal voltage of the buffer.

19. The apparatus as recited in claim 16, wherein the apparatus is implemented in an integrated circuit.

17. (canceled)

20. (canceled)