SELF-BOOTSTRAPPING FIELD EFFECT DIODE STRUCTURES AND METHODS

• US 20100271851A1
• Filed: 01/06/2010
• Published: 10/28/2010
• Est. Priority Date: 09/26/2007
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Lakota Technologies, Inc. (2-Infinity, Inc.)
• Inventors: Ankoudinov, Alexei, Rodov, Vladimir
• Granted Patent: US 8,633,521 B2
• Time in Patent Office: Days
• US Class Current: 363/126
• CPC Class Codes: H01L 27/0811 MIS diodes
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 29/7412 the device being a diode
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.

Claims

1. A semiconductor diode comprising:

first and second field-effect-gated current-conducting devices of opposite respective conductivity types, having respective sources thereof connected together, and each having a respective gate connected to the potential of a respective drift region of the other said MOS-gated device;

said field-effect-gated current-conducting devices each having respective drain terminals, which are externally connected to provide anode and cathode connections respectively;

wherein said devices have no other external electrical connection.

4. The device of claim 1, wherein said first gate electrode is connected to said second external terminal.

5. The device of claim 1, wherein said first conductivity type is n-type, and said first-type majority carriers are electrons.

6. The device of claim 1, wherein said first gate electrode is connected to said second external terminal, and said second gate electrode is connected to said first external terminal.

7. The device of claim 1, wherein said second gate electrode is connected to a first probe node which is fed by said first drift region, and wherein said first probe node is not itself connected to said first external terminal.

8. The device of claim 1, wherein said second gate electrode is connected to a first probe node which is fed by said first drift region, and wherein said first probe node is not itself connected to said first external terminal;

and wherein said first gate electrode is connected to a second probe node which is fed by said second drift region, and wherein said second probe node is not directly connected to said second external terminal.

9. The device of claim 1, wherein said first and second gate electrodes have different respective work function values.

10. The device of claim 1, wherein said first and second gate electrodes are made from polycrystalline semiconductor materials with opposite respective doping types.

11. The device of claim 1, wherein said first and second channels both have a lateral-DMOS configuration.

12. The device of claim 1, wherein said second drift region is substantially lateral, and said first drift region extends vertically downward to a backside drain connection structure.

13. The device of claim 1, wherein said first and second gate electrodes are each insulated from said respective channels.

14. The device of claim 1, wherein both said drift regions extend vertically downward, in separate respective semiconductor crystals, to respective backside drain connection structures.

2. A semiconductor device comprising:

a first semiconductor channel which electrically separates a first semiconductor source of a first conductivity type from a first drift region, and which is gated by a first gate electrode;

a second semiconductor channel which electrically separates a second semiconductor source of a second conductivity type from a second drift region, and which is gated by a second gate electrode;

said first and second sources being electrically connected together;

a first external terminal, which is operatively connected to receive first-type majority carriers through said first drift region, and a second external terminal, which is operatively connected to receive second-type majority carriers through said second drift region;

said first gate electrode being operatively connected to receive a potential which is dependent on the potential of said second drift region, and said second gate electrode being operatively connected to receive a potential which is dependent on the potential of said first drift region;

whereby said first and second terminals provide rectification therebetween.

15. The device of claim 2, wherein said first gate electrode is connected to said second external terminal.

16. The device of claim 2, wherein said first conductivity type is n-type, and said first-type majority carriers are electrons.

17. The device of claim 2, wherein said first gate electrode is connected to said second external terminal, and said second gate electrode is connected to said first external terminal.

18. The device of claim 2, wherein said second gate electrode is connected to a first probe node which is fed by said first drift region, and wherein said first probe node is not itself connected to said first external terminal.

19. The device of claim 2, wherein said second gate electrode is connected to a first probe node which is fed by said first drift region, and wherein said first probe node is not itself connected to said first external terminal;

and wherein said first gate electrode is connected to a second probe node which is fed by said second drift region, and wherein said second probe node is not directly connected to said second external terminal.

20. The device of claim 2, wherein said first and second gate electrodes have different respective work function values.

21. The device of claim 2, wherein said first and second gate electrodes are made from polycrystalline semiconductor materials with opposite respective doping types.

22. The device of claim 2, wherein said first and second channels both have a lateral-DMOS configuration.

23. The device of claim 2, wherein said second drift region is substantially lateral, and said first drift region extends vertically downward to a backside drain connection structure.

24. The device of claim 2, wherein said first and second gate electrodes are each insulated from said respective channels.

25. The device of claim 2, wherein both said drift regions extend vertically downward, in separate respective semiconductor crystals, to respective backside drain connection structures.

3. A merged semiconductor device comprising:

a first field-effect transistor structure, having a first semiconductor channel which electrically separates a first semiconductor source of a first conductivity type from a first drift region, and which is gated by a first gate electrode;

said first drift region supplying first-type majority carriers both to a first drain structure, and also to a first probe node which is electrically separate from said first drain structure;

a second field-effect transistor structure, having a second semiconductor channel which electrically separates a second semiconductor source of a second conductivity type from a second drift region, and which is gated by a second gate electrode;

said second drift region supplying second-type majority carriers at least to a second drain structure;

wherein said second gate electrode is connected to said first probe node, and said first gate electrode is connected to be driven by said second drift region;

said first and second sources being electrically connected together; and

said first and second drains being externally connected to provide rectification therebetween.

26. The device of claim 3, wherein said first gate electrode is connected to said second external terminal.

27. The device of claim 3, wherein said first conductivity type is n-type, and said first-type majority carriers are electrons.

28. The device of claim 3, wherein said first gate electrode is connected to said second external terminal, and said second gate electrode is connected to said first external terminal.

29. The device of claim 3, wherein said second gate electrode is connected to a first probe node which is fed by said first drift region, and wherein said first probe node is not itself connected to said first external terminal.

30. The device of claim 3, wherein said second gate electrode is connected to a first probe node which is fed by said first drift region, and wherein said first probe node is not itself connected to said first external terminal;

and wherein said first gate electrode is connected to a second probe node which is fed by said second drift region, and wherein said second probe node is not directly connected to said second external terminal.

31. The device of claim 3, wherein said first and second gate electrodes have different respective work function values.

32. The device of claim 3, wherein said first and second gate electrodes are made from polycrystalline semiconductor materials with opposite respective doping types.

33. The device of claim 3, wherein said first and second channels both have a lateral-DMOS configuration.

34. The device of claim 3, wherein said second drift region is substantially lateral, and said first drift region extends vertically downward to a backside drain connection structure.

35. The device of claim 3, wherein said first and second gate electrodes are each insulated from said respective channels.

36. The device of claim 3, wherein both said drift regions extend vertically downward, in separate respective semiconductor crystals, to respective backside drain connection structures.

37. A semiconductor device operable as a diode comprising

a. Cathode contact made to a first drain region of the n-type conductivity, operatively coupled to a first source region, first gate region and first probe region;

b. Anode contact made to a second drain region of the p-type conductivity, operatively coupled to a second source region, second gate region and second probe region;

c. The first probe region being connected to the second gate region;

d. The first gate region being connected to the second probe region; and

e. The first source region being connected to the second source region.

38. The device of claim 37, wherein said first drain region and first probe region are the same.

39. The device of claim 37, wherein said first drain region and first probe region are the same, and said second drain region and second probe region are the same.

40. A method for rectifying current from an anode terminal to a cathode terminal, comprising the actions of:

a) when said cathode terminal is more negative than said anode terminal, then sinking current from said anode terminal through a first drift region and a first field-effect-gated channel to an n-type source, and also sourcing current to said cathode terminal from a p-type source through a second field-effect-gated channel and a second drift region;

said n-type and p-type sources being electrically connected together;

said second channel being gated by a second gate electrode which is coupled to said first drift region; and

said first channel being gated by a first gate electrode which is coupled to said second drift region;

to thereby reduce the potential barrier between said source and channel is reduced during forward bias conditions, and increase the potential barrier height during reverse bias conditions.