Reduced complexity array line drivers for 3D matrix arrays
First Claim
1. A method of biasing a nonvolatile memory array, the nonvolatile memory array comprising a first plurality of Y lines, a second plurality of Y lines, a plurality of X lines, a first plurality of two terminal memory cells and a second plurality of two terminal memory cells, wherein each of the first plurality of memory cells is coupled to one of the first plurality of Y lines and one of the plurality of X lines and each of the second plurality of memory cells is coupled to one of the second plurality of Y lines and one of the plurality of X lines, the method comprising:
- driving substantially all of the first plurality and second plurality of Y lines to a Y line unselect voltage; and
driving at least one selected Y line of the first plurality of Y lines to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage.
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Accused Products
Abstract
A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or second plurality of Y lines and one of the plurality of X lines, respectively. Substantially all of the first plurality and second plurality of Y lines are driven to a Y line unselect voltage. At least one selected Y line of the first plurality of Y lines is driven to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage.
119 Citations
56 Claims
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1. A method of biasing a nonvolatile memory array, the nonvolatile memory array comprising a first plurality of Y lines, a second plurality of Y lines, a plurality of X lines, a first plurality of two terminal memory cells and a second plurality of two terminal memory cells, wherein each of the first plurality of memory cells is coupled to one of the first plurality of Y lines and one of the plurality of X lines and each of the second plurality of memory cells is coupled to one of the second plurality of Y lines and one of the plurality of X lines, the method comprising:
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driving substantially all of the first plurality and second plurality of Y lines to a Y line unselect voltage; and driving at least one selected Y line of the first plurality of Y lines to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A nonvolatile memory array, comprising:
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a first plurality of Y lines; a first plurality of Y line drivers electrically connected to the first plurality of Y lines; a first bias generating circuit electrically connected to a first source of each of the first plurality of Y line drivers, wherein the first bias generating circuit is coupled to a Y line select voltage and a Y line unselect voltage; a first decoder that controls the first plurality of Y line drivers; a second plurality of Y lines; a second plurality of Y line drivers electrically connected to the second plurality of Y lines; a second bias generating circuit electrically connected to a second source of each of the second plurality of Y line drivers, wherein the second bias generating circuit is coupled to the Y line select voltage and the Y line unselect voltage; a second decoder that controls the second plurality of Y line drivers; a plurality of X lines; a plurality of X line drivers electrically connected to the plurality of X lines, wherein the plurality of X line drivers comprise a X line select voltage node and a X line unselect voltage node; and a plurality of memory cells, wherein each memory cell is a two-terminal memory cell, and wherein each memory cell is electrically connected to one of the either the first or second plurality of Y lines and one of the plurality of X lines. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A nonvolatile memory array, comprising:
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a first plurality of Y lines; a first plurality of Y line drivers electrically connected to the first plurality of Y lines, each of the first plurality of Y line drivers is electrically connected to a Y line select voltage node; a first bias generating circuit electrically connected to a first body of each of the first plurality of Y line drivers, wherein the first bias generating circuit is coupled to a Y line select biasing voltage and a Y line unselect biasing voltage; a first decoder that controls the first plurality of Y line drivers; a second plurality of Y lines; a second plurality of Y line drivers electrically connected to the second plurality of Y lines, each of the second plurality of Y line drivers is electrically connected to a second Y line select voltage node; a second bias generating circuit electrically connected to a second body of each of the second plurality of Y line drivers, wherein the second bias generating circuit is coupled to the Y line select biasing voltage and the Y line unselect biasing voltage; a second decoder that controls the second plurality of Y line drivers; a plurality of X lines; a plurality of X line drivers electrically connected to the plurality of X lines, wherein the plurality of X line drivers comprise a X line select voltage node and a X line unselect voltage node; and a plurality of memory cells, wherein each memory cell is a two-terminal memory cell, and wherein each memory cell is electrically connected to one of the either the first or second plurality of Y lines and one of the plurality of X lines. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A nonvolatile memory array, comprising:
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a plurality of Y lines comprising a plurality of Y drainage groups; a plurality of Y line drivers electrically connected to the plurality of Y lines, wherein each of the plurality of Y line drivers provides a Y line select voltage and a Y line unselect voltage; a decoder that controls the plurality of Y line drivers; a plurality of X lines; a plurality of X line drivers electrically connected to the plurality of X lines, wherein the plurality of X line drivers comprise a X line select voltage node and a X line unselect voltage node; a plurality of memory cells, wherein each memory cell is a two-terminal memory cell, and wherein each memory cell is electrically connected to one of the plurality of Y lines and one of the plurality of X lines; and a plurality of drainage X lines, wherein each of the plurality of drainage X lines is exclusively electrically connected to a Y drainage group of the plurality of Y drainage groups. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
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Specification