System and Method for Delaying a Signal Communicated from a System to at Least One of a Plurality of Memory Circuits

• US 20100271888A1
• Filed: 04/28/2010
• Published: 10/28/2010
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 8,154,935 B2
• Time in Patent Office: Days
• US Class Current: 365/194
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.

Claims

1. A sub-system, comprising:

a component in communication with a plurality of memory circuits and a system, the component operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay.

2. The sub-system of claim 1, wherein the signal includes a control or address signal.

3. The sub-system of claim 1, wherein the signal includes a data signal.

4. The sub-system of claim 1, wherein the delay is fixed.

5. The sub-system of claim 1, wherein the delay is variable.

6. The sub-system of claim 1, wherein the signal is associated with an operation selected from the group consisting of a write operation, a read operation, a refresh operation, a mode register write operation, a mode register read operation, an activate operation, and a precharge operation.

7. The sub-system of claim 6, wherein the delay associated with the operation is fixed.

8. The sub-system of claim 6, wherein the delay associated with the operation is variable.

9. The sub-system of claim 1, wherein the delay includes a cumulative delay associated with at least one control or address signal, and at least one data signal.

10. The sub-system of claim 9, wherein the at least one control or address signal is received from the system, and the at least one data signal is received from at least one of the memory circuits.

11. The sub-system of claim 8, wherein the delay is a function of the signal.

12. The sub-system of claim 8, wherein the delay is a function of a previous signal.

13. The sub-system of claim 8, wherein different delays are utilized in association with different signals.

14. The sub-system of claim 1, wherein the component that is operable to carry out the delay is selected from the group consisting of a register, an advanced memory buffer (AMB), a component positioned on at least one dual in-line memory module (DIMM), and a memory controller.

15. The sub-system of claim 1, wherein the component that is operable to carry out the delay includes an interface circuit for interfacing the plurality of memory circuits and the system.

16. The sub-system of claim 1, wherein the delay results in a time shifting of the signal back in time with respect to at least one other signal.

17. The sub-system of claim 1, wherein the delay results in a time shifting of the signal forward in time with respect to at least one other signal.

18. A method, comprising:

receive a signal from a system; and

communicating the signal to at least one of a plurality of memory circuits after a delay.

19. A sub-system, comprising:

a component in communication with a plurality of memory circuits and a system, the component operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.