METHODS AND APPARATUS FOR EXTENDING THE EFFECTIVE THERMAL OPERATING RANGE OF A MEMORY

• US 20100271894A1
• Filed: 07/01/2010
• Published: 10/28/2010
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Roy E. Scheuerlein, Tyler Thorp
• Inventors: Scheuerlein, Roy E., Thorp, Tyler
• Granted Patent: US 8,004,919 B2
• Time in Patent Office: Days
• US Class Current: 365/211
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.

Claims

1. Apparatus comprising:

a thermal sensor on a memory integrated circuit (“

IC”

) ; and

a heating element coupled to the thermal sensor and adapted to heat the memory IC in response to a signal from the thermal sensor.

2. The apparatus of claim 1, wherein the thermal sensor includes a current output temperature sensor.

3. The apparatus of claim 1, wherein the thermal sensor includes at least one of a voltage output sensor, a Brokaw cell, a bi-polar junction transistor-based temperature sensor, a thermocouple, a resistance temperature device, and a thermistor.

4. The apparatus of claim 1, wherein the thermal sensor is integrated in the memory IC.

5. The apparatus of claim 1, wherein the thermal sensor includes a plurality of thermal sensors distributed on the memory IC.

6. The apparatus of claim 1, wherein the heating element includes a resistive heating element.

7. The apparatus of claim 1, wherein the heating element is integrated in the memory IC.

8. The apparatus of claim 1, wherein the heating element includes a plurality of heating elements distributed on the memory IC.

9. The apparatus of claim 1, further including a circuit coupled to the heating element and the thermal sensor and adapted to allow a temperature value to be selected as a threshold below which the heating element is activated.

10. A system comprising:

a non-volatile memory array on an integrated circuit (“

IC”

); and

a thermal regulation circuit integrated on the IC, wherein the thermal regulation circuit is adapted to maintain the memory array at a predefined threshold temperature.

11. The system of claim 10, wherein the non-volatile memory array includes a three dimensional memory array.

12. The system of claim 11, wherein the thermal regulation circuit is disposed on multiple planes of the three dimensional memory array.

13. The system of claim 10, wherein the thermal regulation circuit includes a thermal sensor and a heating element coupled to the thermal sensor.

14. The system of claim 13, wherein the non-volatile memory array includes a three dimensional memory array, and the thermal sensor and the heating element are disposed on different planes of the three dimensional memory array.

15. Apparatus for thermal regulation of a non-volatile three dimensional memory IC, the apparatus comprising:

a current output temperature sensor integrated into a non-volatile three dimensional memory IC; and

a resistive heating element coupled to the current output temperature sensor and adapted to heat the memory IC in response to a signal from the current output temperature sensor indicating that the memory IC is at a temperature below a desired threshold temperature.

16. The apparatus of claim 15, wherein the current output temperature sensor includes a plurality of current output temperature sensors distributed on the three dimensional memory IC.

17. The apparatus of claim 15, wherein the current output temperature sensor is disposed on multiple planes of the three dimensional memory array.

18. The apparatus of claim 15, wherein the resistive heating element includes a plurality of resistive heating elements distributed on the three dimensional memory IC.

19. The apparatus of claim 15, wherein the resistive heating element is disposed on multiple planes of the three dimensional memory array.

20. A memory integrated circuit (“

IC”

) comprising;

a control circuit that provides a first output signal when a temperature of the memory IC is above a predetermined temperature, and a second output signal when the temperature of the memory IC is below the predetermined temperature; and

a heating element adapted to heat the memory IC when the control circuit provides the second output signal.

21. The memory IC of claim 20, wherein the control circuit comprises a temperature transducer that provides an output signal proportional to temperature.

22. The memory IC of claim 21, wherein the temperature transducer comprises one or more of a current output temperature sensor, a voltage output sensor, a Brokaw cell, a bi-polar junction transistor-based temperature sensor, a thermocouple, a resistance temperature device, and a thermistor.

23. The memory IC of claim 21, wherein the control circuit further comprises a resistor coupled to the temperature transducer.

24. The memory IC of claim 21, wherein the control circuit further comprises an operational amplifier having a first input terminal coupled to the temperature transducer, and a second input terminal coupled to a reference voltage.

25. The memory IC of claim 24, wherein the control circuit further comprises a resistor coupled to the first input terminal of the operational amplifier.

26. The memory IC of claim 20, wherein the heating element comprises a resistive heating element.

27. The memory IC of claim 20, wherein the heating element comprises a plurality of resistive heating elements.

28. The memory IC of claim 20, further comprising a enable/disable circuit adapted to disable the control circuit when the memory IC operates in a low power mode.

29. The memory IC of claim 20, further comprising a enable/disable circuit adapted to enable the control circuit when the memory IC operates under line power, and to disable the control circuit when the memory IC operates under battery power.

30. The memory IC of claim 20, further comprising a enable/disable circuit adapted to enable the control circuit when the memory IC:

(1) exhibits a predetermined number of read errors;

(2) operates in an error recovery mode; and

/or (3) operates in a safe mode.

31. The memory IC of claim 20, further comprising a circuit adapted to delay access to the memory IC until the memory IC operates in a predetermined temperature range.

32. The memory IC of claim 20, further comprising a memory cell comprising a diode designed to operate above the predetermined temperature.

33. The memory IC of claim 20, wherein the memory IC comprises a three-dimensional memory array.