SHIFT REGISTER APPARATUS
First Claim
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1. A shift register apparatus, comprising:
- a plurality of shift registers connected in serial, each of the shift registers having a first input terminal and an output terminal, wherein the output terminal of an i-th shift register is coupled to the first input terminal of an (i+1)-th shift register, i is a positive integer, and the i-th shift register comprises;
a first transistor, having a gate receiving a first clock signal, and a first drain/source receiving a first voltage;
a second transistor, having a gate serving as the first input terminal of the i-th shift register and coupled to the output terminal of an (i−
1)-th shift register, a first drain/source coupled to a second drain/source of the first transistor, and a second drain/source coupled to a second voltage;
a capacitor, having a first terminal coupled to the second drain/source of the first transistor, and a second terminal coupled to the second voltage;
a third transistor, having a gate coupled to the first terminal of the capacitor, a first drain/source receiving a second clock signal, and a second drain/source serving as the output terminal of the i-th shift register; and
a fourth transistor, having a gate coupled to the gate of the third transistor, a first drain/source coupled to the second drain/source of the third transistor, and a second drain/source coupled to the second voltage,wherein the first transistor and the third transistor are respectively a first-type transistor, and the second transistor and the fourth transistor are respectively a second-type transistor.
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Abstract
A shift register apparatus is provided. Each of shift registers within the shift register apparatus of the present invention is only constituted by a few of active and passive elements without using conventional digital logic elements, and even the passive element are not required at some conditions. Therefore, the layout area occupied/consumed by each of the shift registers of the present invention is relatively smaller than that of the conventional shift register constituted by a CMOS D-flip-flop, and thus a fabrication cost can be reduced.
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17 Claims
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1. A shift register apparatus, comprising:
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a plurality of shift registers connected in serial, each of the shift registers having a first input terminal and an output terminal, wherein the output terminal of an i-th shift register is coupled to the first input terminal of an (i+1)-th shift register, i is a positive integer, and the i-th shift register comprises; a first transistor, having a gate receiving a first clock signal, and a first drain/source receiving a first voltage; a second transistor, having a gate serving as the first input terminal of the i-th shift register and coupled to the output terminal of an (i−
1)-th shift register, a first drain/source coupled to a second drain/source of the first transistor, and a second drain/source coupled to a second voltage;a capacitor, having a first terminal coupled to the second drain/source of the first transistor, and a second terminal coupled to the second voltage; a third transistor, having a gate coupled to the first terminal of the capacitor, a first drain/source receiving a second clock signal, and a second drain/source serving as the output terminal of the i-th shift register; and a fourth transistor, having a gate coupled to the gate of the third transistor, a first drain/source coupled to the second drain/source of the third transistor, and a second drain/source coupled to the second voltage, wherein the first transistor and the third transistor are respectively a first-type transistor, and the second transistor and the fourth transistor are respectively a second-type transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification