DATA STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM INCORPORATING DATA STORAGE DEVICE

• US 20100274953A1
• Filed: 04/21/2010
• Published: 10/28/2010
• Est. Priority Date: 04/23/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JEONG, Sang Kyoo, JO, Myung Hyun, LEE, Tae Hack, PARK, Chan Ik
• Granted Patent: US 8,478,928 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device comprises a plurality of memory devices and a memory controller. The memory controller exchanges data with the memory devices via a plurality of channels. The memory controller decodes an external command to generate a driving power mode and accesses the memory devices according to the driving power mode.

Claims

1. A storage device, comprising:

a plurality of memory devices; and

a memory controller that exchanges data with the memory devices via a plurality of channels, decodes a command received from another device to determine a driving power mode, and accesses the memory devices according to the driving power mode.

2. The storage device of claim 1, wherein the driving power mode is encoded in a value corresponding to a residual power amount of a power source.

3. The storage device of claim 2, wherein the memory controller activates a portion or all of the channels according to the driving power mode.

4. The storage device of claim 3, wherein the memory controller adjusts a degree of interleaving of the activated channels according to the driving power mode.

5. The storage device of claim 3, wherein the memory controller adjusts a frequency of a clock signal used to control a rate of data transmission on the activated channels according to the driving power mode.

6. The storage device of claim 1, further comprising a buffer memory buffering data under control of the memory controller.

7. The storage device of claim 6, wherein the memory controller adjusts a frequency of a clock signal used to control the buffer memory according to the driving power mode.

8. The storage device of claim 6, wherein the memory controller comprises a central processing unit decoding the command, and a clock frequency of the central processing unit is adjusted according to the driving power mode.

9. The storage device of claim 1, wherein each of the memory devices comprises a flash memory device, and the memory devices and the memory controller form part of a solid state drive.

10. A data storage device, comprising:

a plurality of memory devices; and

a memory controller that exchanges data with the memory devices via a plurality of channels and adjusts a degree of interleaving or bandwidth of the plurality of channels according to a command received from another device;

wherein the command is a vendor specific command generated in accordance with a basic input/output system (BIOS) configuration value.

11. The data storage device of claim 10, wherein the memory controller decodes the command to generate a driving power mode and activates a portion or all of the channels according to the driving power mode.

12. The data storage device of claim 11, wherein the memory controller adjusts the degree of interleaving of the activated channels according to the driving power mode.

13. The data storage device of claim 11, wherein the memory controller adjusts access start times of the respective activated channels according to the driving power mode.

14. The data storage device of claim 10, further comprising a buffer memory that buffers data under control of the memory controller;

wherein the memory controller adjusts a frequency of a clock for driving the buffer memory according to the driving power mode.

15. The data storage device of claim 10, wherein the memory controller comprises a central processing unit that decodes the command, and wherein a clock frequency of the central processing unit is adjusted according to the driving power mode.

16. The data storage device of claim 10, wherein the memory controller adjusts a clock frequency used to operate activated channels according to the driving power mode.

17. The data storage device of claim 10, wherein each of the memory devices comprises a flash memory device, and wherein the memory devices and the memory controller form part of a solid state drive.

18. An information processing system, comprising:

a host generating a command based on a state of a power source; and

a solid state drive that exchanges data with the host in response to the command and operates at a performance level based on a driving power mode encoded in the command.

19. The information processing system of claim 18, wherein the driving power mode is encoded as a value corresponding to a residual power amount of the power source.

20. The information processing system of claim 18, wherein the host generates the driving power mode based on basic input/output system (BIOS) configuration information.