PHYSICALLY-INDEXED LOGICAL MAP TABLE

• US 20100274961A1
• Filed: 04/22/2009
• Published: 10/28/2010
• Est. Priority Date: 04/22/2009
• Status: Abandoned Application

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Golla, Robert T., Barreh, Jama I., Levy, Howard L.
• Application Number:
  US12/428,457
• Publication Number:
  US 20100274961A1
• Time in Patent Office: Days
• US Class Current: 711/108
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

Techniques and systems are described herein to maintain a mapping of logical to physical registers—for example, in the context of a multithreaded processor that supports renaming. A mapping unit may have a plurality of entries, each of which stores rename information for a dedicated one of a set of physical registers available to the processor for renaming. This physically-indexed mapping unit may support multiple threads, and may comprise a content-addressable memory (CAM) in certain embodiments. The mapping unit may support various combinations of read operations (to determine if a logical register is mapped to a physical register), write operations (to create or modify one or more entries containing mapping information), thread flush operations, and commit operations. More than one of such operations may be performed substantially simultaneously in certain embodiments.

Claims

1. An apparatus, comprising:

a processor, comprising;

a set of physical registers available to the processor as rename registers; and

a mapping unit having a plurality of entries, each of which is dedicated to a respective one of the set of physical registers and is configured to store rename information indicative of a mapping between a) a register within a set of logical registers that are specified by instructions being executed by the processor and b) the respective one of the set of physical registers that is dedicated to that entry.

2. The apparatus of claim 1, wherein the number of the plurality of entries in the mapping unit that are configured to store rename information is equal to the number of registers in the set of physical registers, and wherein the mapping unit includes a content-addressable memory.

3. The apparatus of claim 1, wherein the number of the plurality of entries in the mapping unit is less than the number of registers in the set of logical registers multiplied by a total number of threads supported by the processor, and wherein the mapping unit includes a content-addressable memory.

4. The apparatus of claim 1, wherein the mapping unit includes a content-addressable memory, and wherein the processor is multithreaded.

5. The apparatus of claim 4, wherein, in response to a given instruction in a current thread of the processor specifying a source register, the processor is configured to perform a read operation on the mapping unit to determine whether the source register has been renamed, wherein in response to the read operation, the mapping unit is configured to compare the current thread and the source register with values stored in each of the plurality of entries;

and

wherein the mapping unit, in response to detecting a match between the given instruction and one of the plurality of entries, is configured to output an indication of the physical register corresponding to the matching entry, the physical register being the register to which the source register has been renamed.

6. The apparatus of claim 4, wherein, in response to a destination of a given instruction in a current thread of the processor being renamed, the processor is configured to perform a write operation to the mapping unit;

wherein, in response to the write operation, the mapping unit is configured to;

update any entries in the mapping unit that match the destination of the given instruction and the current thread; and

write a set of information into a given one of the plurality of entries in the mapping unit, wherein the set of information includes information indicative of the destination of the given instruction and information indicative of a current thread, and wherein the given entry is dedicated to the physical register to which the destination of the given instruction has been renamed.

7. The apparatus of claim 4, wherein, in response to receiving an indication of a flush of a thread, the mapping unit is configured to invalidate any of the plurality of entries storing information corresponding to the thread.

8. The apparatus of claim 4, wherein, in response to a given renamed instruction being committed by the processor, the mapping unit is configured to invalidate an entry that corresponds to a physical register to which a destination of the given renamed instruction has been renamed.

9. The apparatus of claim 8, wherein the mapping unit is configured to invalidate the entry by:

receiving an indication of the physical register to which the destination of the given instruction has been renamed; and

performing a decode operation to determine which of the plurality of entries to invalidate.

10. The apparatus of claim 1, wherein various ones of the set of physical registers are configured to store integer results, and wherein various ones of the set of physical registers are configured to store floating-point results.

11. A method, comprising:

a multithreaded computer processor performing a read operation from a mapping unit to determine whether a source of an instruction within a first thread of the processor has been renamed, wherein the computer processor includes a set of physical registers that constitutes the set of available rename registers;

wherein the mapping unit includes a plurality of entries that are configured to store rename information, wherein each entry is dedicated to a respective one of the set of physical registers and the rename information in each entry is indicative of a mapping between a) a logical register specified by an instruction being executed by the processor and b) the respective one of the set of physical registers dedicated to that entry.

12. The method of claim 11, wherein the number of entries in the mapping unit that are configured to store rename information is equal to the number of registers in the set of physical registers, and wherein the mapping unit includes a content-addressable memory.

13. The method of claim 11, wherein each entry in the mapping unit is configured to store at least a first value indicative of a logical register, a second value indicative of a thread of the computer processor, and a third value indicative of whether the entry is valid, and wherein said performing the read operation includes the mapping unit:

performing a comparison with all entries in the mapping unit to determine whether any entries constitute a match, wherein a determination that a given entry in the mapping unit is a match is based at least in part upon a) the first value of the given entry matching the source of the instruction b) the second value of the given entry matching the first thread, and c) the third value in the given entry indicating that data in the given entry is valid.

14. The method of claim 13, wherein said performing the read operation further includes the mapping unit:

in response to a determining that a match exists with respect to a first of the plurality of entries, outputting a value indicative of the physical register corresponding to the first entry.

15. The method of claim 11, wherein the multithreaded computer processor is configured to perform six substantially simultaneous read operations from the mapping unit to determine whether sources of instructions within the first thread and a second thread have been renamed.

16. A method, comprising:

upon a determination that a destination of a first instruction in a first thread of a multithreaded computer processor is to be renamed, the computer processor performing a write operation to a mapping unit, wherein the computer processor includes a set of physical registers that constitutes the set of available rename registers, and wherein the mapping unit includes a plurality of entries configured to store rename information, wherein each of the plurality of entries is dedicated to a respective one of the set of physical registers and the rename information in each entry is indicative of a mapping between a) a logical register specified by an instruction within the instruction stream of the processor and b) the respective one of the set of physical registers that is dedicated to that entry.

17. The method of claim 16, wherein the number of entries in the mapping unit that are configured to store rename information is equal to the number of registers in the set of physical registers, and wherein the mapping unit includes a content-addressable memory.

18. The method of claim 16, wherein said performing the write operation includes the mapping unit:

updating any existing entries that match the destination of the first instruction and the first thread.

19. The method of claim 18, wherein said performing the write operation further includes the mapping unit:

writing a set of information into a given one of the plurality of entries, wherein the given entry corresponds to the physical register to which the destination of the first instruction has been renamed, and wherein the set of information includes information indicative of the destination of the first instruction and information indicative of the first thread.

20. The method of claim 16, further comprising the multithreaded computer processor performing at least one other write operation substantially simultaneously with said performing.