SYSTEMS, METHODS, AND APPARATUSES FOR PARALLEL COMPUTING

• US 20100274972A1
• Filed: 12/23/2009
• Published: 10/28/2010
• Est. Priority Date: 11/24/2008
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rozhkov, Sergey A., Shishlov, Sergey Yu., Khartikov, Denis M., Butuzov, Alexander V., Gnatyuk, Vladimir L., Khvatov, Roman A., Babayan, Boris, Scherbinin, Sergey P., Pentkovski, Vladimir M.
• Application Number:
  US12/646,815
• Publication Number:
  US 20100274972A1
• Time in Patent Office: Days
• US Class Current: 711/125
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

Systems, methods, and apparatuses for parallel computing are described. In some embodiments, a processor is described that includes a front end and back end. The front includes an instruction cache to store instructions of a strand. The back end includes a scheduler, register file, and execution resources to execution the strand'"'"'s instructions.

Claims

1. An apparatus comprising:

a front end comprising,

a first instruction cache to store instructions belonging to a first plurality of strands; and

a back end coupled to the front end comprising,

a first scheduler to receive the first plurality of strands and schedule the instructions of the first plurality of strands in a first set of execution resources, wherein the instruction resources execute the instructions,

a register file coupled to the execution resources to provide data to the execution resources for the execution of the instructions of the first plurality of strands.