Flexible vector modes of operation for SIMD processor
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Abstract
In addition to the usual modes of SIMD processor operation, where corresponding elements of two source vector registers are used as input pairs to be operated upon by the execution unit, or where one element of a source vector register is broadcast for use across the elements of another source vector register, the new system provides several other modes of operation for the elements of one or two source vector registers. Improving upon the time-costly moving of elements for an operation such as DCT, the present invention defines a more general set of modes of vector operations. In one embodiment, these new modes of operation use a third vector register to define how each element of one or both source vector registers are mapped, in order to pair these mapped elements as inputs to a vector execution unit. Furthermore, the decision to write an individual vector element result to a destination vector register, for each individual element produced by the vector execution unit, may be selectively disabled, enabled, or made to depend upon a selectable condition flag or a mask bit.
128 Citations
59 Claims
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1-44. -44. (canceled)
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45. An execution unit for use in a computer system for operably pairing elements of two vector operands based on a user-defined mapping and carrying out a vector operation defined in a computer instruction on said paired elements, the execution unit comprising:
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first and second input vector registers for holding respective first and second source vector operands on which said vector operation is to be carried out, wherein each of said first and second input vector registers holds a plurality of vector elements of a predetermined size, each of said plurality of vector elements defining one of a plurality of vector element positions; at least one control vector register; means for loading said first and second input vector registers, and said at least one control vector register; a plurality of operators associated respectively with said plurality of vector element positions for carrying out said vector operation; means for selecting and pairing any element of said first input vector register with any element of said second input vector register as inputs to said plurality of operators for each vector element position in dependence on said at least one control vector register; and a destination vector register for holding results of said vector operation on an element-by-element basis. - View Dependent Claims (46, 47, 48, 49, 50)
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51. An apparatus for mapping first and second source vector elements, in accordance with a control vector, and performing arithmetic or logical operations on said mapped first and second source vector elements in parallel, the apparatus comprising:
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a vector register file including a plurality of vector registers with a plurality of read data ports and at least one write data port, wherein said first source vector, said second source vector and said control vector can be accessed in parallel; addresses for said plurality of read data ports and said at least one write port are coupled to respective source and destination fields of a vector instruction; a first select logic coupled to a respective read port for said first source vector for mapping said first source vector elements in accordance with said control vector; a second select logic coupled to a respective read port for said second source vector for mapping said second source vector elements in accordance with said control vector; a vector operation unit including a plurality of computing elements coupled to outputs of said first select logic and said second select logic for performing said arithmetic or logical operations on vector elements in parallel as defined by said vector instruction; and means for storing the output of said vector operation unit in a destination vector register in said vector register file. - View Dependent Claims (52, 53, 54)
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55. A method for flexibly pairing vector elements of a first source vector and a second source vector, in accordance with a third source vector as a control vector, and performing a vector operation, the method comprising:
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storing said first source vector; storing said second source vector; storing said control vector; selecting, in accordance with a first designated field of each vector element of said control vector, one of the vector elements of said first source vector; selecting, in accordance with a second designated field of each vector element of said control vector, one of the vector elements of said second source vector; performing said vector operation on respective vector elements of said selected first source vector and said selected second source vector to produce respective resulting elements of an output vector; and storing said output vector, said output vector being the same size as said first source vector and said second source vector. - View Dependent Claims (56, 57, 58, 59)
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Specification