Apparatus and Method for Performing SIMD Multiply-Accumulate Operations

• US 20100274990A1
• Filed: 09/17/2009
• Published: 10/28/2010
• Est. Priority Date: 10/08/2008
• Status: Active Grant

• Current Assignee: U-Blox AG (u-blox Holding AG)
• Original Assignee: U-Blox AG (u-blox Holding AG)
• Inventors: Bruce, Richard Edward, Symes, Dominic Hugo, Wilder, Mladen
• Granted Patent: US 8,443,170 B2
• Time in Patent Office: Days
• US Class Current: 712/22
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/3893 controlled in tandem, e.g. multiplier-accumulator

Abstract

An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry. In response to those control signals, the SIMD data processing circuitry performs the plurality of iterations of a multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply-accumulate results. This mechanism provides a particularly energy efficient mechanism for performing SIMD multiply-accumulate operations, as for example are required for FIR filter processes.

Claims

1. A data processing apparatus comprising:

SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements;

instruction decoder circuitry coupled to said SIMD data processing circuitry and responsive to program instructions to generate said control signals;

said instruction decoder circuitry being responsive to a repeating multiply-accumulate (repeating MAC) instruction having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations M required, to generate control signals to control said SIMD data processing circuitry;

to perform said plurality of iterations of a multiply-accumulate process, each iteration of the multiply-accumulate process comprising performing N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements;

for each iteration, to determine N input data elements from said first vector and a single coefficient data element from said second vector to be multiplied with each of the N input data elements during the N multiply-accumulate operations; and

to output N multiply-accumulate results derived from the N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process.

2. A data processing apparatus as claimed in claim 1, wherein the repeating MAC instruction is used to perform an FIR filter operation, and the N multiply-accumulate results produced form N FIR results.

3. A data processing apparatus as claimed in claim 1, wherein the SIMD data processing circuitry has a state machine for determining the N input data elements and the single coefficient data element for each iteration.

4. A data processing apparatus as claimed in claim 3, wherein the number of input data elements in the first vector is at least N+M−

1, and the state machine determines the N input data elements for iteration P by causing a shift operation to be performed with respect to the N data elements used for iteration P−

1.

5. A data processing apparatus as claimed in claim 3, wherein the state machine determines a different coefficient data element from said second vector for each iteration.

6. A data processing apparatus as claimed in claim 1, wherein the repeating MAC instruction also has as an input operand a vector of initial multiply-accumulate data elements.

7. A data processing apparatus as claimed in claim 1, wherein no vector of initial multiply-accumulate data elements is specified, and the N multiply-accumulate data elements are set to zero prior to the first iteration of the multiply-accumulate process.

8. A data processing apparatus as claimed in claim 3, wherein the state machine determines the number of iterations M from the scalar value, and asserts a stall signal to one or more components of the data processing apparatus whilst at least one of the plurality of iterations are being performed.

9. A data processing apparatus as claimed in claim 8, wherein the stall signal is asserted during all but one iteration of the plurality of iterations.

10. A data processing apparatus as claimed in claim 1, further comprises a SIMD register bank for storing data elements, the SIMD data processing circuitry accessing said first and second vectors from registers of the SIMD register bank prior to performing said plurality of iterations of the multiply-accumulate process, whereby no further access to the SIMD register bank is required in respect of the first and second vectors during performance of said plurality of iterations of the multiply-accumulate process.

11. A data processing apparatus as claimed in claim 10, wherein the first vector of input data elements has a number of input data elements which is a multiple of N, and the SIMD data processing circuitry accesses said input data elements by accessing multiple registers of the SIMD register bank, each of said multiple registers containing N input data elements.

12. A data processing apparatus as claimed in claim 10, further comprising a multiply-accumulate register for storing N multiply-accumulate data elements.

13. A data processing apparatus as claimed in claim 12, wherein each of the input data elements comprise X bits, each of the coefficient data elements comprise Y bits, and each multiply-accumulate data element stored in the multiply-accumulate register is at least X+Y bits in size.

14. A data processing apparatus as claimed in claim 13, wherein the multiply-accumulate register stores the multiply-accumulate data elements in extended form, the extended form including additional bits used for determining an overflow.

15. A data processing apparatus as claimed in claim 1, wherein:

at least one of the input data elements and the coefficient data elements are complex numbers that comprise real and imaginary parts;

each iteration of the multiply-accumulate process comprises performing N complex multiply-accumulate operations in parallel in order to produce N complex multiply-accumulate data elements; and

the N multiply-accumulate results output are complex numbers.

16. A data processing apparatus as claimed in claim 15, wherein both the input data elements and the coefficient data elements are complex numbers that comprise real and imaginary parts.

17. A data processing apparatus as claimed in claim 15, wherein each complex multiply-accumulate operation involves performance of a sequence of multiply, add and subtract operations in order to produce real and imaginary parts of the corresponding complex multiply-accumulate data element.

18. A data processing apparatus as claimed in claim 15, wherein the coefficient data elements are complex numbers, and in each iteration the complex coefficient data element is conjugated before the N complex multiply-accumulate operations are performed.

19. A data processing apparatus as claimed in claim 1, wherein the multiply-accumulate operations are multiply-subtract operations.

20. A data processing apparatus as claimed in claim 3, wherein one of the control signals produced by the instruction decoder circuitry specifies whether rounding is required, and if rounding is required the state machine is arranged to cause a rounding increment to be injected into each multiply-accumulate operation performed in one of said plurality of iterations.

21. A data processing apparatus as claimed in claim 1, wherein one of the control signals produced by the instruction decoder circuitry specifies whether the multiply-accumulate data elements to be produced are saturating or non-saturating, and accumulate circuitry within the SIMD data processing circuitry is configured dependent on said control signal.

22. A data processing apparatus as claimed in claim 1, wherein said scalar value is less than or equal to N.

23. A data processing apparatus as claimed in claim 22, wherein if N+Q iterations are required, where Q is less than or equal to N, then a first repeating MAC instruction has a scalar value indicating N iterations, and is followed by a further repeating MAC instruction having a scalar value indicating Q iterations and identifying as a vector of initial multiply-accumulate data elements the N multiply-accumulate results generated by the SIMD data processing circuitry in response to the first repeating MAC instruction.

24. A data processing apparatus as claimed in claim 1, wherein if said scalar value as specified by the repeating MAC instruction is larger than a maximum number of iterations that can be performed, then the scalar value is set equal to said maximum number and said SIMD data processing circuitry performs said maximum number of iterations of said multiply-accumulate process.

25. A data processing apparatus as claimed in claim 1, wherein the instruction decoder circuitry is responsive to a sequence of repeating MAC instructions to generate control signals to control said SIMD data processing circuitry to perform a sequence of multiply-accumulate stages, each multiply-accumulate stage performing said plurality of iterations of said multiply-accumulate process, and at least one multiply-accumulate stage using as an input the N multiply-accumulate results generated by a previous multiply-accumulate stage.

26. A data processing apparatus as claimed in claim 1, wherein the instruction decoder circuitry is responsive to a single repeating MAC instruction to generate control signals to control said SIMD data processing circuitry to perform at least two multiply-accumulate stages, each multiply-accumulate stage performing said plurality of iterations of said multiply-accumulate process, with the input data elements and the coefficient data elements required for each multiply-accumulate stage being determined from the first and second vectors.

27. A data processing apparatus as claimed in claim 25, wherein the multiple multiply-accumulate stages are used to perform repeated MAC operations on complex numbers.

28. A method of processing data using SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements and instruction decoder circuitry coupled to said SIMD data processing circuitry and responsive to program instructions to generate said control signals, said method comprising the steps of:

decoding a repeating multiply-accumulate (repeating MAC) instruction having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations M required, to generate control signals; and

controlling said SIMD data processing circuitry with said control signals to produce multiply-accumulate results by the steps of;

performing said plurality of iterations of a multiply-accumulate process, each iteration of the multiply-accumulate process comprising performing N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements;

for each iteration, determining N input data elements from said first vector and a single coefficient data element from said second vector to be multiplied with each of the N input data elements during the N multiply-accumulate operations; and

outputting N multiply-accumulate results derived from the N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process.

29. A virtual machine implementation of a data processing apparatus, said virtual machine implementation being responsive to a repeating multiply-accumulate (repeating MAC) instruction having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations M required, to produce multiply-accumulate results by the steps of:

performing said plurality of iterations of a multiply-accumulate process, each iteration of the multiply-accumulate process comprising performing N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements;

for each iteration, determining N input data elements from said first vector and a single coefficient data element from said second vector to be multiplied with each of the N input data elements during the N multiply-accumulate operations; and

outputting N multiply-accumulate results derived from the N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process.

30. A data processing apparatus comprising:

SIMD data processing means for performing data processing operations in parallel on multiple data elements in response to control signals; and

instruction decoder means coupled to said SIMD data processing means for generating said control signals in response to program instructions;

wherein said instruction decoder means, in response to a repeating multiply-accumulate (repeating MAC) instruction having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations M required, generates control signals to control said SIMD data processing means to produce multiply-accumulate results by the steps of;

performing said plurality of iterations of a multiply-accumulate process, each iteration of the multiply-accumulate process comprising performing N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements;

for each iteration, determining N input data elements from said first vector and a single coefficient data element from said second vector to be multiplied with each of the N input data elements during the N multiply-accumulate operations; and

outputting N multiply-accumulate results derived from the N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process.