POWER MANAGEMENT METHOD AND RELATED CHIPSET AND COMPUTER SYSTEM

• US 20100275045A1
• Filed: 11/23/2009
• Published: 10/28/2010
• Est. Priority Date: 04/24/2009
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Huang, Cheng-Wei, Qin, Shuang-Shuang
• Granted Patent: US 8,250,393 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A power management method for use in a computer system having a processor, a power management module and a phase lock loop circuit (PLL) is provided. The power management module is coupled to a plurality of peripheral modules and the computer system and the processor are capable of being operated in a working state and power saving states. The method includes the following. When the computer system is operated in the working state and the processor is entered into a lowest power consumption state among the power saving states, states of the peripheral modules are detected to determine whether a specific condition has been matched. If the specific condition is matched, the processor is directed to a control state to control the PLL according to a control state configuration.

Claims

1. A power management method for use in a computer system having a processor, a power management module coupled to a plurality of peripheral modules and a phase lock loop circuit (PLL), wherein the computer system and the processor are capable of being operated in a working state and a plurality of power saving states, comprising:

when the computer system is operated in the working state and the processor is entered into a lowest power consumption state among the power saving states, detecting states of the peripheral modules to determine whether a specific condition is matched; and

if following detection, the states of the peripheral modules match to the specific condition, directing the processor to a control state to control the PLL according to a control state configuration.

2. The power management method of claim 1, wherein the step of directing the processor to a control state to control the PLL according to a control state configuration further comprises:

sending a first control signal for gating a clock output of the PLL when the control state is configured as a first control state; and

sending a second control signal to power down the PLL when the control state is configured as a second control state.

3. The power management method of claim 1, wherein the step of directing the processor to a control state to control the PLL according to a control state configuration further comprises:

sending a second control signal and a third control signal to power down the PLL and stopping output of a source clock generator corresponded to the PLL when the control state is configured as a second control state.

4. The power management method of claim 1, further comprising:

providing a control state configuration option to configure the control state in a basic input/output system (BIOS).

5. The power management method of claim 1, wherein each of the peripheral modules has a low power consumption state and the step of detecting states of the peripheral modules to determine whether the specific condition is matched is determining whether predetermined peripheral modules among the peripheral modules are operated in the corresponding low power consumption states.

6. The power management method of claim 5, wherein the predetermined peripheral modules comprise a memory controller, a graphic controller, a USB controller and a SATA controller, and the power management module determines the specific condition is matched when the following conditions have been satisfied:

the memory controller is operated in a self-refresh mode;

the graphic controller is operated in a snapshot mode;

the USB controller configures USB devices to be operated in a D3 mode; and

the SATA controller configures SATA devices to be operated in a partial/slumber mode.

7. The power management method of claim 1, wherein the step of detecting states of the peripheral modules to determine whether the specific condition is matched is performed when the peripheral modules are idle for a predetermined time period.

8. The power management method of claim 2, wherein when detecting that a wake-up event has occurred in the control state, performing a resume procedure to direct the processor to resume to the lowest power consumption state and when the control state is configured as the first control state, the resume procedure stops gating the clock output of the PLL.

9. The power management method of claim 2, wherein when detecting that a wake-up event has occurred in the control state, performing a resume procedure to direct the processor to resume to the lowest power consumption state and when the control state is configured as the second control state, the resume procedure activates the output of the clock of a source clock generator corresponded to the PLL.

10. The power management method of claim 3, wherein when detecting that a wake-up event has occurred in the control state, performing a resume procedure to direct the processor to resume to the lowest power consumption state and when the control state is configured as the second control state and the third control signal has been sent, the resume procedure activates the output of the clock of a source clock generator corresponded to the PLL and activates the PLL when the source clock generator PLL has been activated.

11. A chipset coupled to a clock generator and a processor, comprising:

a phase lock loop circuit (PLL), generating at least one second clock signal according to a first clock signal generated by the clock generator;

a gating unit coupled to the PLL, controlling the output of the second clock signal generated by the PLL;

a plurality of peripheral modules, each of which having a low power consumption state; and

a power management module coupled to the gating unit, the peripheral modules and the PLL,

wherein when the processor enters into a lowest power consumption state among the power saving states, the power management module detects states of the peripheral modules to determine whether a specific condition is matched and if following detection, the states of the peripheral modules match to the specific condition, directs the processor to a control state to control the PLL according to a control state configuration.

12. The chipset of claim 11, wherein the power management module sends a first control signal to the gating unit for gating the second clock signal output of the PLL when the control state is configured as a first control state and sends a second control signal to power down the PLL when the control state is configured as a second control state.

13. The chipset of claim 11, wherein the power management module sends a second control signal and a third control signal to the PLL and the clock generator respectively for powering down the PLL and stopping output of a source clock generator corresponded to the PLL when the control state is configured as a second control state

14. The chipset of claim 11, wherein each of the peripheral modules has a low power consumption state and the power management module further determines whether the specific condition has been matched by determining whether predetermined peripheral modules among the peripheral modules are operated in the corresponding low power consumption states.

15. The chipset of claim 14, wherein the predetermined peripheral modules comprise a memory controller, a graphic controller, a USB controller and a SATA controller, and the power management module determines the specific condition is matched when the following conditions have been satisfied:

the memory controller is operated in a self-refresh mode;

the graphic controller is operated in a snapshot mode;

the USB controller configures USB devices to be operated in a D3 mode; and

the SATA controller configures SATA devices to be operated in a partial/slumber mode.

16. The chipset of claim 11, wherein the power management module further detects states of the peripheral modules to determine whether the specific condition is matched when the peripheral modules are idle for a predetermined time period.

17. The chipset of claim 12, wherein when detecting that a wake-up event has occurred in the control state, the power management module further performs a resume procedure to direct the processor to resume to the lowest power consumption state and when the control state is configured as the first control state, the resume procedure stops gating the second clock signal output of the PLL via the gating unit.

18. The chipset of claim 12, wherein when detecting that a wake-up event has occurred in the control state, the power management unit performs a resume procedure to direct the processor to resume to the lowest power consumption state and when the control state is configured as the second control state, the resume procedure activates the output of the clock of the source clock generator corresponded to the PLL.

19. The chipset of claim 13, wherein when detecting that a wake-up event has occurred in the control state, the power management unit performs a resume procedure to direct the processor to resume to the lowest power consumption state and when the control state is configured as the second control state, the resume procedure activates the output of the clock of the source clock generator corresponded to the PLL and when the source clock generator PLL has been activated, activates the PLL.

20. A computer system, comprising:

a clock generator, generating a first clock signal;

a processor; and

a chipset coupled to the clock generator and the processor, comprising;

a phase lock loop circuit (PLL), generating at least one second clock signal according to the first clock signal;

a gating unit coupled to the PLL, controlling the output of the second clock signal generated by the PLL;

a plurality of peripheral modules, each of which having a low power consumption state; and

a power management module coupled to the gating unit, the peripheral modules and the PLL,

wherein when the computer system is operated in a working state and the processor enters into a lowest power consumption state among the power saving states, the power management module detects states of the peripheral modules to determine whether a specific condition is matched and if following detection, the states of the peripheral modules match to the specific condition, directs the processor to a control state to control the PLL according to a control state configuration.

21. The computer system of claim 20, wherein the power management module sends a first control signal to the gating unit for gating the second clock signal output of the PLL when the control state is configured as a first control state and sends a second control signal to power down the PLL when the control state is configured as a second control state.

22. The computer system of claim 20, wherein the power management module sends a second control signal and a third control signal to the PLL and the clock generator respectively for powering down the PLL and stopping output of the clock of the clock generator corresponded to the PLL when the control state is configured as a second control state.

23. The computer system of claim 20, wherein each of the peripheral modules has a low power consumption state and the power management module further determines whether the specific condition has been matched by determining whether predetermined peripheral modules among the peripheral modules are operated in the corresponding low power consumption states.

24. The computer system of claim 23, wherein the predetermined peripheral modules comprise a memory controller, a graphic controller, a USB controller and a SATA controller, and the power management module determines the specific condition is matched when the following conditions have been satisfied:

the memory controller is operated in a self-refresh mode;

the graphic controller is operated in a snapshot mode;

the USB controller configures USB devices to be operated in a D3 mode; and

the SATA controller configures SATA devices to be operated in a partial/slumber mode.