POWER CONSERVATION IN VERTICALLY-STRIPED NUCA CACHES

• US 20100275049A1
• Filed: 04/24/2009
• Published: 10/28/2010
• Est. Priority Date: 04/24/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Balakrishnan, Ganesh, Krishna, Anil
• Granted Patent: US 8,103,894 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments that dynamically conserve power in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are vertically distributed across multiple banks. To conserve power, the computing devices generally turn off groups of banks, in a sequential manner according to different power states, based on the access latencies of the banks. The computing devices may first turn off groups having the greatest access latencies. The computing devices may conserve additional power by turning of more groups of banks according to different power states, continuing to turn off groups with larger access latencies before turning off groups with the smaller access latencies.

Claims

1. A method, comprising:

enabling the operation of a plurality of banks of a non-uniform cache access (NUCA) cache, wherein ways of the cache are vertically distributed across multiple banks of the plurality;

disabling, sequentially, individual banks of the plurality to conserve power of the NUCA cache, wherein the sequential disabling comprises firstly turning off individual banks with the greatest access latencies of banks of the NUCA cache and lastly turning off individual banks with the least access latencies, wherein further the disabling of the individual banks comprises turning off banks of the plurality grouped via discrete power states.

2. The method of claim 1, further comprising:

determining whether data of an individual bank are different from data of memory associated with the individual bank and writing the data to the associated memory if the data are different.

3. The method of claim 2, further comprising:

disabling the individual bank upon completion of the writing.

4. The method of claim 3, further comprising:

marking a partial tag array of the NUCA cache to prevent usage of the disabled individual bank.

5. The method of claim 1, further comprising:

selecting a power state via execution of instructions stored in a tangible medium of a computer.

6. The method of claim 5, wherein the instructions, when executed by a processor of the computer, are configured to monitor an amount of energy of a battery of the computer.

7. The method of claim 5, wherein the instructions, when executed by a processor of the computer, are configured to select the power state based upon inactivity of the NUCA cache.

8. An apparatus, comprising:

a plurality of banks of a non-uniform cache access (NUCA) cache, wherein ways are vertically distributed across multiple banks of the plurality;

a plurality of switches configured to turn off groups of banks of the plurality of banks, wherein banks are aggregated to the groups based on access latencies; and

a state selector, coupled to the plurality of switches, to select different power states of the NUCA cache, wherein the state selector is arranged to turn off groups of banks with the larger access latencies before turning off other groups with smaller access latencies.

9. The apparatus of claim 8, further comprising an activity monitor to monitor activity of the NUCA cache, wherein the state selector is arranged to select the different power states based on the monitored activity, wherein the apparatus is configured to sequentially turn on groups of banks with the smaller access latencies before turning on groups with the larger access latencies.

10. The apparatus of claim 8, further comprising a multi-cache controller coupled to the NUCA cache and a second NUCA cache and a second plurality of switches, the multi-cache controller configured to select different power states of the NUCA cache and the second NUCA cache based upon an input from the state selector.

11. The apparatus of claim 8, further comprising a power controller coupled to a core and the NUCA cache, the power controller configured to monitor and control power of the core and the NUCA cache.

12. The apparatus of claim 11, further comprising a second core and a second NUCA cache, wherein the power controller is configured to turn off the second core and all groups of banks in the second NUCA cache while at least one group of the NUCA cache continues to operate.

13. The apparatus of claim 8, further comprising a tag array manager to maintain tags of the NUCA cache and prevent the searching of banks that are turned off.

14. The apparatus of claim 13, further comprising a data manager to write out data of a group of banks to enable the state selector to select a different power state.

15. The apparatus of claim 8, wherein the state selector comprises a state machine.

16. A computer program product comprising a tangible computer readable storage medium including instructions that, when executed by at least one processor:

search ways of a plurality of banks of a non-uniform cache access (NUCA) cache, wherein the ways are vertically distributed across multiple banks of the NUCA cache; and

sequentially turn off groups of banks of the plurality of banks, wherein each of the groups comprises banks aggregated based on access latencies of banks to the at least one processor, wherein further the sequence comprises turning off groups with larger access latencies before turning off groups with smaller access latencies.

17. The computer program product of claim 16, further comprising instructions that monitor an amount of power remaining in a battery to enable the sequential turning off of groups.

18. The computer program product of claim 16, further comprising instructions that mark locations in a partial tag array to prevent use of the locations, wherein the locations correspond to banks turned off.

19. The computer program product of claim 18, further comprising instructions that unmark the locations in the partial tag array to enable use of the locations when banks corresponding to the locations are turned on.

20. The computer program product of claim 16, wherein the instructions that sequentially turn off groups of banks comprise instructions of an operating system.