LOAD ADAPTIVE EMI REDUCTION SCHEME FOR SWITCHING MODE POWER SUPPLY

• US 20100275052A1
• Filed: 04/24/2009
• Published: 10/28/2010
• Est. Priority Date: 04/24/2009
• Status: Active Grant

• Current Assignee: Fremont Micro Devices Corporation
• Original Assignee: Evergreen Micro Devices Co., Ltd.
• Inventors: Ku, Matthew Man Ho
• Granted Patent: US 8,201,012 B2
• Time in Patent Office: Days
• US Class Current: 713/501
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

The present invention relates to a frequency jittering device and method, and a switching power supply employing such frequency jittering device. Said method comprises: S1 generating a variable logic number; S2 generating a delay signal; S3 generating a PWM control signal according to the variable logic number and the delay signal; S4 generating an output signal according to the PWM control signal; and S5 generating a clock signal with variable frequency according to the output signal; wherein, the clock signal is fed back to update the variable logic number, and a jittering clock signal modified in each clock cycle is produced. The benefit of the present invention is not only can apply small low cost EMI filter but also can keep the noise floor level low enough at light load condition.

Claims

1. A frequency jittering device, wherein, it comprises:

a Variable State Machine for generating a variable logic number;

a Time delay generator for generating a delay signal;

a Digital Control Pulse Density Generator for generating a PWM control signal according to the variable logic number and the delay signal;

a PWM Control Current Source for generating an output signal according to the PWM control signal; and

a Current Control Oscillator for generating a clock signal with variable frequency according to the output signal;

wherein, the clock signal is fed back to the Variable State Machine to update the variable logic number, and a jittering clock signal modified in each clock cycle is produced.

2. The frequency jittering device according to claim 1, wherein, the Digital Control Pulse Density Generator further comprises:

a ring oscillator realized with multiple of inverters connected in series;

a combinational logic circuit for generating different high-low density pulse train; and

a multiplexer implemented with switch network controlled by a decoder;

wherein, the PWM control signal is realized by inserting the delay signal into the ring oscillator and receiving the variable logic number from the decoder.

3. The frequency jittering device according to claim 2, wherein, the Digital Control Pulse Density Generator is used to create a series of pulse with different high-low density according to the variable logic number.

4. The frequency jittering device according to claim 3, wherein, the pulse density function P_density is expressed by equation (1):

5. The frequency jittering device according to claim 4, wherein, T_H(n)+T_L(n) is always a constant value.

6. The frequency jittering device according to claim 4, wherein, the PWM control signal D_PWM is realized by adding the delay signal generated from Time Delay Generator into Pulse density function and is given by equation (2):

7. The frequency jittering device according to claim 6, wherein, the magnitude of output signal generated from PWM control current source is defined by equation (3).

I_c(D_PWM)=I_s×

D_PWM  

 

Equation (3)

where I_s is a predefined constant current source.

8. The frequency jittering device according to claim 6, wherein, the percentage swing of the frequency of the jittering clock signal can be expressed by equation (4):

9. A frequency jittering method, wherein, it comprising:

S1 generating a variable logic number;

S2 generating a delay signal;

S3 generating a PWM control signal according to the variable logic number and the delay signal;

S4 generating an output signal according to the PWM control signal; and

S5 generating a clock signal with variable frequency according to the output signal;

wherein, the clock signal is fed back to update the variable logic number, and a jittering clock signal modified in each clock cycle is produced.

10. The frequency jittering method according to claim 9, wherein, said step S3 further comprises creating a series of pulse with different high-low density according to the variable logic number.

11. The frequency jittering method according to claim 10, wherein, The pulse density function P_density is expressed by equation (1):

12. The frequency jittering method according to claim 11, wherein, T_H(n)+T_L(n) is always a constant value.

13. The frequency jittering method according to claim 11, wherein, the PWM control signal D_PWM is realized by adding the delay signal generated from Time Delay Generator into Pulse density function and is given by equation (2):

14. The frequency jittering method according to claim 13, wherein, the magnitude of output signal is defined by equation (3).

I_c(D_PWM)=I_s×

D_PWM  

 

Equation (3)

where I_s is a predefined constant current source.

15. The frequency jittering method according to claim 13, wherein, the percentage swing of the frequency of the jittering clock signal can be expressed by equation (4):

16. A switching power supply which comprising an input circuit, wherein, it also comprises:

a feed back control loop formed by a Transformer;

a Control;

a Power Switch with drain connected to the primary winding of the Transformer, source grounded and gate connected to the Control, and an output circuit connected to the secondary winding of the Transformer;

Wherein, the Control is used to regulate the output voltage based on the jittering frequency with output adaptive frequency swing generated inside and a feedback signal provided by the feed back control loop.

17. The switching power supply according to claim 16, wherein, the Control further comprises a Frequency Jittering device and a PWM Control, the Frequency Jittering device is used to generate a jittering frequency with output adaptive frequency swing based on a feedback signal provided by the feed back control loop;

the PWM Control is used to vary the ratio of Power Switch on-off period and thus regulates the output voltage based on the jittering frequency with output adaptive frequency swing from the Frequency Jittering device and the feedback signal provided by the feed back control loop.

18. The switching power supply according to claim 17, wherein, the frequency jittering device further comprises:

a Variable State Machine for generating a variable logic number;

a Time delay generator for generating a delay signal;

a Digital Control Pulse Density Generator for generating a PWM control signal according to the variable logic number and the delay signal;

a PWM Control Current Source for generating an output signal according to the PWM control signal; and

a Current Control Oscillator for generating a clock signal with variable frequency according to the output signal;

wherein, the clock signal is fed back to the Variable State Machine to update the variable logic number, and a jittering clock signal modified in each clock cycle is produced.

19. The switching power supply according to claim 18, wherein, the Digital Control Pulse Density Generator further comprises:

a ring oscillator realized with multiple of inverters connected in series;

a combinational logic circuit for generating different high-low density pulse train; and

a multiplexer implemented with switch network controlled by a decoder;

wherein, the PWM control signal is realized by inserting the delay signal into the ring oscillator and receiving the variable logic number from the decoder.

20. The switching power supply according to claim 18, wherein, the Digital Control Pulse Density Generator is used to create a series of pulse with different high-low density according to the variable logic number;

wherein, the pulse density function P_density is expressed by equation (1);