GATE ELECTRODES FOR MILLIMETER-WAVE OPERATION AND METHODS OF FABRICATION

• US 20100276698A1
• Filed: 04/29/2009
• Published: 11/04/2010
• Est. Priority Date: 04/29/2009
• Status: Active Grant

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Heikman, Sten, Moore, Marcia
• Granted Patent: US 8,741,715 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

A transistor device having a tiered gate electrode fabricated with methods using a triple layer resist structure. The triple layer resist stack is deposited on a semiconductor structure. An exposure pattern is written onto the resist stack using an e-beam writer, for example. The exposure dose is non-uniform across the device. Portions of the three resist layers are removed with a sequential development process, resulting in tiered resist structure. A conductive material is deposited to form the gate electrode. The resulting “Air-T” gate also has a three-tiered structure. The fabrication process is well-suited for the production of gates small enough for use in millimeter wave devices.

Claims

1. A transistor comprising:

a semiconductor structure;

a protective layer on said semiconductor structure having an opening exposing a portion of said semiconductor structure; and

a gate electrode, comprising;

a contact portion in said opening and

electrically contacting said semiconductor structure;

a first-tier portion on said contact portion and extending laterally on said protective layer on at least one side of said contact portion, said first-tier section comprising sidewalls having a generally concave shape; and

a second-tier portion on said first-tier portion opposite said contact portion and extending laterally beyond at least one edge of said first-tier portion.

2. The transistor of claim 1, further comprising a source electrode on one side of said gate electrode and a drain electrode on the other side of said gate electrode, said source and drain electrodes electrically contacting said semiconductor structure.

3. The transistor of claim 1, wherein said contact portion is recessed into said semiconductor structure.

4. The transistor of claim 1, wherein said first-tier portion extends laterally on said protective layer on both sides of said contact portion.

5. The transistor of claim 1, wherein said second-tier portion extends laterally beyond both edges of said first-tier portion.

6. The transistor of claim 1, said first-tier section comprising sidewalls that angle away from said contact portion.

7. The transistor of claim 1, said semiconductor structure comprising a barrier layer, said contact portion electrically contacting said barrier layer.

8. The transistor of claim 1, said semiconductor structure comprising Group-III nitride semiconductor materials.

9. The transistor of claim 1, said protective layer comprising silicon nitride (SiN).

10. A method of fabricating a gate electrode on a semiconductor structure, comprising:

depositing a resist layer that comprises an inner layer, a middle layer, and an outer layer on said semiconductor structure, said inner layer closest to said semiconductor structure;

removing selected portions of said resist layer in sequence starting with said outer layer; and

depositing a conductive material in the space left after said removal of selected portions.

11. The method of claim 10, said inner and outer layers comprising electron beam resist materials.

12. The method of claim 10, said middle layer comprising a resist material different from the material of said inner and outer layers, said middle layer material associated with a developer that does not develop said outer and inner layers.

13. The method of claim 10, further comprising, after depositing said resist layer, exposing a pattern on said resist layer.

14. The method of claim 13, wherein an electron beam is used to expose said pattern.

15. The method of claim 14, wherein the dose of exposure from said electron beam is non-uniform over said resist layer.

16. The method of claim 13, further comprising developing at least a portion of said outer layer such that at least a portion of said middle layer is exposed.

17. The method of claim 16, further comprising developing at least a portion of said middle layer such that a portion of said inner layer is exposed.

18. The method of claim 17, wherein a portion of said middle layer is removed that is laterally beyond the edge of the remaining portion of said outer layer, forming an undercut feature.

19. The method of claim 18, further comprising developing at least a portion of said inner layer such that at least a portion of said semiconductor structure is exposed, such that the remaining portion of said inner layer has sidewalls that are generally concave and angle away from the center of said gate electrode.

20. The method of claim 10, wherein said conductive material is deposited using an evaporation process and the orientation of said resist layer is varied during deposition.

21. A method for manufacturing a semiconductor device, comprising:

forming a semiconductor structure;

depositing a protective layer on said semiconductor structure;

etching a portion of said protective layer to expose a portion of said semiconductor device;

depositing an inner resist layer on said protective layer and the exposed portion of said semiconductor structure;

depositing a middle resist layer on said inner resist layer;

depositing an outer resist layer on said middle resist layer;

exposing a pattern on said resist layers with an electron beam, said electron beam outputting a varying exposure dosage during said writing;

developing said outer resist layer to expose a portion of said middle resist layer;

developing said middle resist layer to expose a portion of said inner resist layer;

developing said inner resist layer to expose a portion of said semiconductor structure; and

depositing a metal in the area left by the developing of said outer, middle, and inner resist layers.

22. The method of claim 21, wherein said protective layer comprises silicon nitride (SiN).

23. The method of claim 21, wherein said inner and outer resist layers comprise ZEP-520A and said middle resist layer comprises polymethylglutarimide (PMGI).

24. The method of claim 23, wherein said inner resist layer is deposited to be approximately 200-800 nm thick, said middle resist layer is deposited to be approximately 500-600 nm thick, and said outer resist layer is deposited to be approximately 200 nm thick.

25. The method of claim 23, wherein said developing of said outer resist layer is done with a mix of methyl ethyl ketone and methyl isobutyl ketone (MEK:

MIBK), said developing of said middle resist layer is done with a tetramethylammonium hydroxide (TMAH) based developer, and said developing of said inner resist layer is done with amyl acetate.

26. The method of claim 21, wherein said inner resist layer comprises polymethylmethacrylate-950k (PMMA-950k), said middle resist layer comprises PMGI, and said outer layer comprises co-PMMA.

27. The method of claim 21, wherein during said exposure, said electron beam has a highest exposure dosage in the center of said resist layers and an exposure dosage that decreases with distance moving away from the center on both sides.

28. The method of claim 21, wherein said inner resist layer is developed such that its sidewalls are generally concave and angle away from the center of the device.

29. The method of claim 21, wherein said etching a portion of said protective layer to expose a portion of said semiconductor device is done before depositing said resist layers.

30. The method of claim 21, wherein said etching a portion of said protective layer to expose a portion of said semiconductor device is done after developing said inner resist layer.