Avalanche capability improvement in power semiconductor devices having dummy cells around edge of active area

• US 20100276728A1
• Filed: 04/29/2009
• Published: 11/04/2010
• Est. Priority Date: 04/29/2009
• Status: Active Grant

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Granted Patent: US 8,072,000 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A structure of power semiconductor device having dummy cells around edge of active area is disclosed. The UIS test result of said improved structure shows that failed site after UIS test randomly located in active area which means avalanche capability of the semiconductor power device is enhanced by implementation of the dummy cells.

Claims

1. A vertical semiconductor power MOSFET device comprising a plurality of semiconductor power cells with each cell comprising a trenched gate surrounded by a source region with first type conductivity in active area encompassed in a body region with second type conductivity above a drain region disposed on a bottom surface of a low-resistivity substrate with first type conductivity, wherein said MOSFET cell further comprising:

an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower doping concentration than the substrate;

a first insulating layer serving as gate oxide lining the inner surface of openings for trench gates;

a second insulating layer functioning as thick contact oxide interlayer covering top surface of the epitaxial layer;

a plurality of trench source-body contacts filled with tungsten plugs and opened through the second insulating layer and extending into the body region;

at least one dummy cell without source region formed at the edge of active area near by gate metal pad and gate metal runner.

a source metal layer connected to the source regions and the body regions via the trench source-body contacts;

a gate metal layer served as gate metal pad for wire bonding, and connected to gate metal runner;

a drain metal layer formed on a bottom surface of the substrate.

2. The MOSFET of claim 1, wherein gate metal runner also serving as metal field plate is deposited over P-body region in termination area.

3. The MOSFET of claim 1, wherein gate metal runner also serving as metal field plate is deposited over deep guard ring in termination area.

4. The MOSFET of claim 1, wherein termination area comprises multiple trench floating rings.

5. The MOSFET of claim 1, wherein the MOSFET cells are designed to be closed cell structure.

6. The MOSFET of claim 1, wherein the MOSFET cells are designed to be stripe cell structure.

7. The MOSFET of claim 1, wherein gate metal pad connected to single or multiple gate runners.

8. The MOSFET of claim 1, wherein poly zener diode is formed underneath gate metal pad.

9. A vertical semiconductor power IGBT device comprising a plurality of semiconductor power cells with each cell comprising a trenched gate surrounded by an emitter region with first type conductivity in active area encompassed in a base region with second type conductivity, wherein said IGBT cell further comprising:

a substrate heavily doped with the second type conductivity;

a first epitaxial layer grown on the substrate and heavily doped with the first type conductivity;

a second epitaxial layer grown on the first epitaxial layer and lightly doped with the first type conductivity;

a first insulating layer serving as gate oxide lining the inner surface of openings for trench gates;

a second insulating layer functioning as thick contact oxide interlayer covering top surface of the epitaxial layer;

a plurality of trench emitter-base contacts filled with tungsten plugs and opened through the second insulating layer and extending into the body region;

at least one dummy cell without emitter region formed at the edge of active area near by gate metal pad and gate metal runner.

an emitter metal layer connected to the emitter regions and the base regions via the trench emitter-base contacts;

a gate metal layer served as gate metal pad for wire bonding, and connected to gate metal runner;

a back metal layer formed on a bottom surface of the substrate.

10. The IGBT of claim 9, wherein said IGBT is PT IGBT.

11. The IGBT of claim 9, wherein said IGBT is NPT IGBT.

12. The IGBT of claim 9, wherein gate metal runner also serving as metal field plate is deposited over deep guard ring in termination area.

13. The IGBT of claim 9, wherein termination area comprises multiple trench floating rings.

14. The IGBT of claim 9, wherein the IGBT cells are designed to be closed cell structure.

15. The IGBT of claim 9, wherein the IGBT cells are designed to be stripe cell structure.

16. The IGBT of claim 9, wherein gate metal pad connected to single or multiple gate runners.

17. The IGBT of claim 9, wherein poly zener diode is formed underneath gate metal pad.