Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure

• US 20100276792A1
• Filed: 05/01/2009
• Published: 11/04/2010
• Est. Priority Date: 05/01/2009
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Cho, NamJu, Shin, HanGil, Chi, HeeJo
• Granted Patent: US 8,018,034 B2
• Time in Patent Office: Days
• US Class Current: 257/660
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/29 characterised by the material , e.g. carbon interlayer dielectrics H01L23/5329
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device has a substrate containing a conductive layer. An interconnect structure is formed over the substrate and electrically connected to the conductive layer. A semiconductor component is mounted to the substrate. An encapsulant is deposited over the semiconductor component and interconnect structure. A channel is formed in the encapsulant to expose the interconnect structure. Solder paste is deposited in the channel prior to forming the shielding layer. A shielding layer is formed over the encapsulant and semiconductor component. The shielding layer can be conformally applied over the encapsulant and semiconductor die and into the channel. The shielding layer extends into the channel and electrically connects to the interconnect structure. A docking pin is formed on the shielding layer, which extends into the channel and electrically connects to the interconnect structure. A chamfer area is formed around a perimeter of the shielding layer.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate containing a conductive layer;

forming a solder bump over the substrate and electrically connected to the conductive layer;

mounting a semiconductor die to the substrate;

depositing an encapsulant over the semiconductor die and solder bump;

forming a channel in the encapsulant to expose the solder bump; and

forming a shielding layer over the encapsulant and semiconductor die, the shielding layer extending into the channel and electrically connecting to the solder bump to provide isolation from inter-device interference.

2. The method of claim 1, further including depositing solder paste in the channel prior to forming the shielding layer.

3. The method of claim 1, further including forming a chamfer area around the shielding layer.

4. The method of claim 1, further including planarizing the encapsulant and a backside of the semiconductor die.

5. The method of claim 1, further including forming a docking pin on the shielding layer which extends into the channel and electrically connects to the solder bump.

6. The method of claim 1, further including conformally applying the shielding layer over the encapsulant and semiconductor die and into the channel.

7. The method of claim 1, further including forming the channel in the encapsulant using a saw blade, film assist molding, or laser ablation.

8. A method of manufacturing a semiconductor device, comprising:

providing a substrate containing a conductive layer;

forming an interconnect structure over the substrate and electrically connected to the conductive layer;

mounting a semiconductor component to the substrate;

depositing an encapsulant over the semiconductor component and interconnect structure;

forming a channel in the encapsulant to expose the interconnect structure; and

forming a shielding layer over the encapsulant and semiconductor component, the shielding layer being electrically connected to the interconnect structure to provide isolation from inter-device interference.

9. The method of claim 8, further including depositing solder paste in the channel prior to forming the shielding layer.

10. The method of claim 8, further including forming a chamfer area around the shielding layer.

11. The method of claim 8, wherein the interconnect structure includes a solder bump, conductive pillar, stud bump, or micro bump.

12. The method of claim 8, further including forming a docking pin on the shielding layer which extends into the channel and electrically connects to the interconnect structure.

13. The method of claim 8, further including conformally applying the shielding layer over the encapsulant and semiconductor die and into the channel.

14. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

mounting a semiconductor component to the substrate;

depositing an encapsulant over the semiconductor component;

forming a channel in the encapsulant; and

forming a shielding layer over the encapsulant and semiconductor component.

15. The method of claim 14, further including forming an interconnect structure over the substrate and electrically connected to a conductive layer within the substrate, the shielding layer being electrically connected to the interconnect structure.

16. The method of claim 14, wherein the interconnect structure includes a solder bump, conductive pillar, stud bump, or micro bump.

17. The method of claim 14, further including depositing solder paste in the channel prior to forming the shielding layer.

18. The method of claim 14, further including forming a docking pin on the shielding layer which extends into the channel and electrically connects to the interconnect structure.

19. The method of claim 14, further including conformally applying the shielding layer over the encapsulant and semiconductor die and into the channel.

20. The method of claim 14, further including distributing heat generated by the semiconductor component across the shielding layer.

21. A semiconductor device, comprising:

a substrate containing a conductive layer;

an interconnect structure formed over the substrate and electrically connected to the conductive layer;

a semiconductor component mounted to the substrate;

an encapsulant deposited over the semiconductor component and interconnect structure;

a channel formed in the encapsulant to the interconnect structure; and

a shielding layer formed over the encapsulant and semiconductor component, the shielding layer being electrically connected to the interconnect structure to provide isolation from inter-device interference.

22. The semiconductor device of claim 21, further including a chamfer area formed around a perimeter of the shielding layer.

23. The semiconductor device of claim 21, wherein the interconnect structure includes a solder bump, conductive pillar, stud bump, or micro bump.

24. The semiconductor device of claim 21, further including a docking pin formed on the shielding layer, the docking pin extending into the channel and electrically connecting to the interconnect structure.

25. The semiconductor device of claim 21, wherein the shielding layer is conformally applied over the encapsulant and semiconductor die and into the channel.