SEMICONDUCTOR TEST SYSTEM AND METHOD

• US 20100277196A1
• Filed: 05/01/2009
• Published: 11/04/2010
• Est. Priority Date: 05/01/2009
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: Cambridge Silicon Radio Limited (Qualcomm, Inc.)
• Inventors: Walsh, James Paul
• Granted Patent: US 8,278,958 B2
• Time in Patent Office: Days
• US Class Current: 324/754.11
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371

Abstract

A method of testing semiconductor devices, the method includes the steps of making a first set of electrical connections to a first set of devices to allow a first set of tests to be performed on that set of devices and concurrently making a second set of electrical connections to a second set of devices to allow a second set of tests to be performed on the second set of devices, wherein the first and second sets of tests are different, and concurrently performing the first set of tests on the first set of devices and the second set of tests on the second set of devices.

Claims

1. A method of testing semiconductor devices, the method comprising the steps of:

(a) making a first set of electrical connections to a first set of devices to allow a first set of tests to be performed on that set of devices and concurrently making a second set of electrical connections to a second set of devices to allow a second set of tests to be performed on the second set of devices, wherein the first and second sets of tests are different; and

(b) concurrently performing the first set of tests on the first set of devices and the second set of tests on the second set of devices.

2. The method according to claim 1, wherein steps (a) and (b) are repeated a plurality of times and wherein the devices forming the first and second sets of devices are different for each repetition.

3. The method according to claim 1, wherein the first and second sets of tests are discrete.

4. The method according to claim 1, wherein the steps further comprise the step of storing data relating to the results of the tests.

5. The method according to claim 4, wherein the steps further comprise the step of correlating data from the first and second sets of tests on each device.

6. The method according to claim 1, wherein the devices are located on a wafer.

7. The method according to claim 6, wherein the wafer is a bare wafer.

8. The method according to claim 1, wherein the devices are WLCSP devices.

9. The method according to claim 1, wherein the devices are packaged devices.

10. A contact device for making contact between test equipment and semiconductor devices, comprising:

a first set of test positions for making a first set of electrical contacts with each of a first set of the devices, the first set of electrical contacts allowing a first set of tests to be performed on the first set of devices; and

a second set of test positions for concurrently making a second set of electrical contacts with each of a second set of the devices, the second set of electrical contacts allowing a second set of tests to be performed on the second set of devices;

wherein the first and second sets of tests are different and the first and second sets of devices do not overlap.

11. The contact device according to claim 10, wherein the first and second sets of tests are discrete.

12. The contact device according to claim 10, wherein the contact device is a probe card for contacting devices on a wafer.

13. The contact device according to claim 12, wherein the devices are WLCSP devices.

14. The contact device according to claim 12, wherein the wafer is a bare wafer.

15. The contact device according to claim 10, wherein the contact device is a Device Interface Board for contacting packaged devices.

16. A system, comprising:

an automated piece of test equipment; and

a contact device associated with the automated piece of test equipment, the contact device comprising;

a first set of test positions for making a first set of electrical contacts with each of a first set of the devices, the first set of electrical contacts allowing a first set of tests to be performed on the first set of devices; and

a second set of test positions for concurrently making a second set of electrical contacts with each of a second set of the devices, the second set of electrical contacts allowing a second set of tests to be performed on the second set of devices;

wherein the first and second sets of tests are different and the first and second sets of devices do not overlap.

17. The system according to claim 16, wherein the first and second sets of tests are discrete.

18. The system according to claim 16, wherein the contact device is a probe card for contacting devices on a wafer.

19. The system according to claim 18, wherein the devices are WLCSP devices.

20. The system according to claim 18, wherein the wafer is a bare wafer.

21. The system according to claim 16, wherein the contact device is a Device Interface Board for contacting packaged devices.

22. The system according to claim 18, further comprising means to move the wafer relative to the probe card to vary the devices of the wafer that comprise the first and second sets of devices.

23. The system according to claim 16, further comprising a processing apparatus to correlate the results of the first and second sets of tests for each device.