SYSTEM AND METHOD IMPLEMENTING SHORT-PULSE PROPAGATION TECHNIQUE ON PRODUCTION-LEVEL BOARDS WITH INCREMENTAL ACCURACY AND PRODUCTIVITY LEVELS

• US 20100277197A1
• Filed: 04/29/2009
• Published: 11/04/2010
• Est. Priority Date: 04/29/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Katopis, George A., Kopcsay, Gerard V., Deutsch, Alina, Surovic, Christopher W., Krabbenhoft, Roger S.
• Granted Patent: US 8,035,409 B2
• Time in Patent Office: Days
• US Class Current: 324/758
• CPC Class Codes: G01R 31/2818 using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors G01R31/2805 takes precedence; printed circuits having, e.g. symbols, test patterns or visualisation means H05K1/0266
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28

Abstract

A system and method for performing a test for characterizing high frequency operation of PCB boards. More particularly, a system and methodology is provided to implement a time-domain short pulse propagation (SPP) technique on the production line, on large, multi-layer, product-level PCB boards, for large volume testing, by people who are not familiar with advanced, delicate, measurement techniques, who need robust test facilities, and cannot afford the time or expense of other lab-type approaches.

Claims

1. A system for testing performance of a multi-level printed circuit board (PCB) having one or more layers of conductors carrying signals at or exceeding Gigahertz frequencies, the testing system comprising:

formed at a layer of said multi-level PCB board, a first conductor line of x length and a second conductor line of y length where x>

y; and

, each first and second conductor line having respective capture pad termination at each end;

a plated via through hole extending between a formed surface test pad connector at said top and bottom surfaces of said PCB for electrically coupling respective first and second capture pad terminations at each line end to a respective surface test pad connector provided at a top and bottom PCB surface, each test pad connector configured for electrical coupling to an RF connector device at said PCB board surface; and

,

a testing apparatus configured for testing said conductor line formed at a PCB layer by inputting signals at a first end of said conducting line via said RF connector device coupled to a first surface test pad connector at a PCB surface and measuring signals at a second end of said conducting line via a second RF connector device coupled to a second surface test pad connector at said PCB surface,

said test apparatus processing said measured signals for modeling performance of said PCB when operating in excess of Gigahertz frequencies, said testing implementing a time-domain Short Pulse Propagation (SPP) technique.

2. The system as claimed in claim 1, further comprising:

formed at a layer of said multi-level PCB board, a capacitor structure having a first a test pad structure formed at a layer being electrically coupled to each end of said capacitor plate structure and configured for electrical coupling to said RF connector device.

3. The system as claimed in claim 1, wherein the testing apparatus comprises:

first and second mounting devices rigidly holding first and second RF connector devices; and

,

indexing means for automatically aligning said multi-level PCB to said first and second RF connector devices for enabling coupling of said RF connector devices to respective surface test pad structures.

4. The system as claimed in claim 1, wherein the testing apparatus comprises:

robotic manipulator including arms holding said first and second RF connector devices, said arms configured for automatic indexed movement to align said first and second RF connector devices to surface test pad structures of said multi-level PCB to enable coupling of said RF connector devices to said respective surface test pad structures.

5. The system as claimed in claim 1, wherein said surface test pad structures of said multi-level PCB comprises one or more mechanical alignment holes, each said RF connector device including a set of guide structures extending therefrom that can be fit in a corresponding said one or more mechanical alignment holes of said surface test pad structure for improved connection.

6. The system as claimed in claim 5, wherein said RF connector device is an SMA connector.

7. The system as claimed in claim 1, wherein said conductor line is a strip line or micro strip transmission line structure.

8. The system as claimed in claim 1, wherein a portion of said plated via through hole extending between a formed surface test pad connector at one of a top or bottom PCB surface and a conductor line capture pad at a signal line layer beneath the PCB surface includes a stub portion, wherein, during said testing, said RF connector devices coupled to a surface test pad connector that minimizes a length of said stub portion.

9. The system as claimed in claim 1, wherein said PCB is a production-level PCB, said test apparatus processing said measured signals for extracting a broadband propagation constant and characteristic impedance of said conductor line structures useful for said performance modeling.

10. The system as claimed in claim 1, wherein said test apparatus processes said measured signals for extracting a broadband attenuation and phase constant of said conductor line structures useful for said performance modeling.

11. A test structure provided for facilitating performance testing of a multi-level printed circuit board (PCB) having one or more layers of conductors carrying signals at or exceeding Gigahertz frequencies, the testing structure comprising:

a first conductor line formed at a layer of said multi-level PCB board, of x length and a second conductor line formed at a same layer of said multi-level PCB board, of y length where x>

y; and

, each first and second conductor line having respective capture pad termination at each end; and

,

a plated via through hole extending between a formed surface test pad connector at a surface of said PCB for electrically coupling respective first and second capture pad terminations at each line end to a respective surface test pad connector provided at a PCB surface, each test pad connector configured for electrical coupling to an RF connector device at said PCB board surface,

wherein a test apparatus models performance of said PCB when operating in excess of Gigahertz frequencies by coupling signals to and from a conductor line via said RF connector device and automatically performing a time domain single pulse propagation measurement of said conductor lines at a PCB layer.

12. The test structure as claimed in claim 11, further comprising:

formed at said same layer of said multi-level PCB board, a capacitor structure having corresponding surface test pad structure being electrically coupled to said capacitor structure through a respective plated via through hole and configured for electrical coupling to said RF connector device.

13. The test structure as claimed in claim 11, wherein said plated via through hole extends between front and back PCB surfaces, a test pad connector provided at both front and back PCB board surfaces.

14. The test structure as claimed in claim 11, wherein said first and second conducting lines are each formed at multiple layers of a PCB, each conductor line at each layer having a respectively formed PTH via connection to a respective test pad connector formed at a PCB surface.

15. The test structure as claimed in claim 13, wherein a portion of said plated via through hole extending between a formed surface test pad connector at one of a top or bottom PCB surface and a conductor line capture pad at a signal line layer beneath the PCB surface includes a stub portion, wherein, during said testing, said RF connector devices coupled to a surface test pad connector that minimizes a length of said stub portion.

16. A method of testing a multi-level printed circuit board (PCB) having one or more layers of conductors carrying signals at or exceeding Gigahertz frequencies, said method comprising:

providing, at a layer of said multi-level PCB board, a test structure comprising;

a first conductor line, of x length and a second conductor line formed at a same layer of y length where x>

y; and

, each first and second conductor line having respective capture pad termination at each end; and

,

a plated via through hole extending between a formed surface test pad connector at a surface of said PCB for electrically coupling respective first and second capture pad terminations at each line end to a respective surface test pad connector provided at a PCB surface, each test pad connector configured for electrical coupling to an RF connector device at said PCB board surface,

automatically coupling a first RF connector device to a respective surface test pad connector via an RF connector device at a first end of a conductor line and a second RF connector device to a respective surface test pad connector at a second end a conductor line;

automatically configuring a testing apparatus for testing said conductor line formed at said layer by inputting signals at a first end of said conducting line via said first RF connector device coupled to a first surface test pad connector at a PCB surface and, measuring signals at a second end of said conducting line via said second RF connector device coupled to a second surface test pad connector at said PCB surface, said testing implementing a time-domain Short Pulse Propagation (SPP) technique; and

,

processing, at a computing device, said measured signals for modeling broadband performance of said PCB when operating in excess of Gigahertz frequencies.

17. The method of testing as claimed in claim 16, wherein said testing apparatus comprises first and second mounting devices rigidly holding said first and second RF connector devices, a platform for engaging said multi-level PCB, and an indexing means carrying for automatically aligning said platform carrying said multi-level PCB with said first and second RF connector devices and automatically coupling said first and second RF connector devices to respective first and second surface test pad structures.

18. The method of testing as claimed in claim 16, wherein the testing apparatus comprises first and second robotic manipulator arms holding respective said first and second RF connector devices, said method further comprising:

automatically coupling said first and second RF connector devices held by said robotic arms to respective surface test pad structures of said multi-level PCB.

19. The method of testing as claimed in claim 16, wherein a portion of said plated via through hole extending between a formed surface test pad connector at one of a top or bottom PCB surface and a conductor line capture pad at a signal line layer beneath the PCB surface includes a stub portion, said method further comprising:

during said testing, coupling said RF connector devices to a surface test pad connector that minimizes a length of said stub portion.

20. The method of testing as claimed in claim 16, wherein said PCB is a production-level PCB, said processing performed at said computing device processing said measured signals for extracting a broadband propagation constant and characteristic impedance of said conductor line structures useful for said performance modeling.

21. The method of testing as claimed in claim 16, wherein said PCB is a production-level PCB, said processing performed at said computing device processing said measured signals for extracting a broadband attenuation and phase constant of said conductor line structures useful for said performance modeling.

22. The method of testing as claimed in claim 16, wherein said processing, at a computing device, further comprises:

screening a conductor line of said test structure using a TDR technique.

23. The method of testing as claimed in claim 16, further comprising:

emulating first or second conductor'"'"'s measurement conditions using a virtual test bench.

24. The method of testing as claimed in claim 21, farther comprising:

compensating the capacitive effect of a via stub portion to thereby extend bandwidth of the broadband PCB measurements.

25. The method of testing as claimed in claim 21, further comprising:

modeling and simulating emulation of a broadband PCB measurement to evaluate sensitivity to process tolerances.