FILTERING ON CURRENT MODE DAISY CHAIN INPUTS

• US 20100277231A1
• Filed: 03/08/2010
• Published: 11/04/2010
• Est. Priority Date: 05/01/2009
• Status: Abandoned Application

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: HURRELL, Christopher Peter, PRICE, Colin, MADHAVAN, Mahesh K., AGRAWAL, Abhishek, MCINTOSH, Colin, GORBOLD, Jeremy
• Application Number:
  US12/719,481
• Publication Number:
  US 20100277231A1
• Time in Patent Office: Days
• US Class Current: 327/564
• CPC Class Codes: B60L 2240/547 Voltage
• CPC Class Codes: B60L 2240/549 Current
• CPC Class Codes: B60L 58/18 of two or more battery modules
• CPC Class Codes: B60L 58/21 having the same nominal voltage
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01M 10/482 for several batteries or cells simultaneously or sequentially
• CPC Class Codes: H02J 7/0013 acting upon several batteries simultaneously or sequentially H02J7/1423 takes precedence
• CPC Class Codes: H02J 7/0048 Detection of remaining charge capacity or state of charge [SOC]
• CPC Class Codes: Y02E 60/10 Energy storage using batteries
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries

Abstract

Embodiments may include a data receiver having input for a current signal. The data receiver may further include a current generator to generate a reference current for comparison against the input current signal. The data receiver may also include a data converter having an input coupled to an intermediate node of the data receiver, the data converter comprising a plurality of cascaded stages with intermediate nodes among the stages.

Claims

1. An integrated circuit comprising:

a data receiver having input for a current signal, the data receiver having a current generator to generate a reference current for comparison against the input current signal;

a data converter having an input coupled to an intermediate node of the data receiver, the data converter comprising a plurality of cascaded data converter stages with intermediate nodes among the data converter stages.

2. The integrated circuit of claim 1, wherein at least one of the data converter stages is an integrator.

3. The integrated circuit of claim 1, wherein at least one of the data converter stages is an inverter.

4. The integrated circuit of claim 1, wherein at least one of the data converter stages is a current-limited inverter having a pair of current generators to generate a first current limit and a second current limit.

5. The integrated circuit of claim 4, wherein the current generators are current mirrors.

7. The integrated circuit of claim 1, wherein the data receiver further comprises two biased transistors extending from a first voltage reference to a second voltage reference, and the data converter input is coupled to an intermediate node between the biased transistors.

8. The integrated circuit of claim 1, wherein the current generator is a current mirror.

9. The integrated circuit of claim 1, further comprising:

a capacitive device coupled to at least one intermediate node among the data converter stages.

10. The integrated circuit of claim 9, wherein the capacitive device limits response of the data converter to glitches on the input current signal

11. The integrated circuit of claim 9, wherein the capacitive device comprises a plurality of capacitors.

12. The integrated circuit of claim 9, wherein the capacitive device comprises a plurality of transistors.

6. The integrated circuit of clam 1, wherein at least one of the data converter stages is a Schmitt-triggered buffer.