MULTI-MODE RADIO FREQUENCY FRONT END MODULE

• US 20100277252A1
• Filed: 05/03/2010
• Published: 11/04/2010
• Est. Priority Date: 05/04/2009
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: RFaxis, Inc. (Skyworks Solutions Incorporated)
• Inventors: GORBACHOV, OLEKSANDR
• Granted Patent: US 8,467,738 B2
• Time in Patent Office: Days
• US Class Current: 333/104
• CPC Class Codes: H01P 1/213 combining or separating two or more different frequencies H01P1/215 takes precedence
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/7209 the gated amplifier being switched from a first band to a second band
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 2203/7227 the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H04B 1/006 using switches for selecting the desired band H04B1/0057 takes precedence
• CPC Class Codes: H04B 1/52 Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa

Abstract

A radio frequency (RF) front end circuit for connecting an antenna to a transceiver having multiple operating modes is disclosed. The circuit has a first transmit input receptive to signals of a first operating mode and a second operating mode from the transceiver. There is also a second transmit input receptive to signals of a third operating mode from the transceiver. The circuit has a first power amplifier for the first and second operating modes, a second power amplifier for the first operating mode, and a third power amplifier for the second and third operating mode. A first switch network selectively interconnects the first transmit input to a one of the second and third power amplifiers.

Claims

1. A radio frequency (RF) front end circuit for connecting an antenna to a transceiver having a first operating mode, a second operating mode, and a third operating mode, comprising:

a first set of transmit ports receptive to signals of the first operating mode and the second operating mode from the transceiver;

a second set of transmit ports receptive to signals of the third operating mode from the transceiver;

a first set of power amplifiers for the first operating mode;

a second set of power amplifiers for the second and third operating modes;

a first switch selectively interconnecting a one of the first set of transmit ports to a one of the first set of power amplifiers and a one of the second set of power amplifiers; and

a second switch selectively interconnecting a different one of the first set of transmit ports to a different one of the first set of power amplifiers and a different one of the second set of power amplifiers.

2. The front end circuit of claim 1, wherein:

the first switch interconnects a one of the second set of transmit ports to a one of the second set of power amplifiers; and

the second switch interconnects a different one of the second set transmit ports to a different one of the second set of power amplifiers.

3. The front end circuit of claim 1, wherein:

the first operating mode is GSM (Global System for Mobile communications);

the second operating mode is EDGE (Enhanced Data rates for GSM Evolution); and

the third operating mode is CDMA.

4. The front end circuit of claim 1, wherein the first and second sets of transmit ports each include a high band port and a low band port.

5. The front end circuit of claim 1, wherein:

the first set of power amplifiers has a non-linear operational characteristic; and

the second set of power amplifiers has a linear operational characteristic.

6. The front end circuit of claim 1, wherein the first and second switches are of a dual-pole, double throw configuration.

7. The front end circuit of claim 6, wherein the first and second switches each include:

a combination input port;

a single input port;

a single output port;

a combination output port; and

a switching network with one or more control lines selectively connecting the combination input port to the combination output port, the single input port to the combination output port, and the combination input port to the single output port, the connections of the switching network being selectable by an activation the one or more control lines.

8. The front end circuit of claim 1, further comprising:

a DC-DC converter coupled to each of the second set of power amplifiers providing bias voltages thereto.

9. The front end circuit of claim 1, further comprising:

a multi-position switch selectively interconnecting the antenna to a single one of the first set of power amplifiers and the second set of power amplifiers.

10. The front end circuit of claim 9, further comprising:

a first set of receive ports relaying signals of the first operating mode and the second operating mode received from the antenna; and

a second set of receive ports relaying signals of the third operating mode received from the antenna.

11. The front end circuit of claim 10, wherein the multi-position switch further selectively interconnects the antenna to a single one of the first set of receive ports and the second set of receive ports.

12. The front end circuit of claim 10, further comprising:

diplexers coupling each output of the second set of power amplifiers and each of the second set of receive ports to the antenna.

13. The front end circuit of claim 12, further comprising:

a first diplexer switch selectively interconnecting one of the output of a first one of the second set of power amplifiers and a first one of the diplexers to the multi-position switch; and

a second diplexer switch selectively interconnecting the output of a second one of the second set of power amplifiers and a second one of the diplexers to the multi-position switch.

14. The front end circuit of claim 13, wherein the diplexer switches, the first switch, the second switch, and the second set of power amplifiers is fabricated on a single die.

15. The front end circuit of claim 12, further comprising:

a first output switch selectively interconnecting a first one of the second set of power amplifiers to one of the diplexers; and

a second output switch selectively interconnecting a second one of the second set of power amplifiers to an other one of the diplexers;

wherein the first set of power amplifiers are selectively interconnected to the antenna by a respective one of the first and second output switches.

16. An RF front end circuit for connecting an antenna to a transceiver having a first operating mode, a second operating mode, and a third operating mode, comprising:

a first transmit input receptive to signals of the first operating mode and the second operating mode from the transceiver;

a second transmit input receptive to signals of the third operating mode from the transceiver;

a first power amplifier for the first and second operating mode;

a second power amplifier for the first operating mode;

a third power amplifier for the second and third operating mode; and

a first switch network selectively interconnecting the first transmit input to a one of the second and third power amplifiers.

17. The front end circuit of claim 16, wherein:

the first operating mode is GSM (Global System for Mobile communications);

the second operating mode is EDGE (Enhanced Data rates for GSM Evolution); and

the third operating mode is CDMA.

18. The front end circuit of claim 16, wherein the first and second switches are of a dual-pole, double throw configuration.

19. The front end circuit of claim 18, wherein the first and second switches each include:

a combination input port;

a single input port;

a single output port;

a combination output port; and

a switching network with one or more control lines selectively connecting the combination input port to the combination output port, the single input port to the combination output port, and the combination input port to the single output port, the connections of the switching network being selectable by an activation the one or more control lines.

20. The front end circuit of claim 16, further comprising:

a DC-DC converter coupled to each of the second set of power amplifiers providing bias voltages thereto.

21. The front end circuit of claim 16, further comprising:

a multi-position switch selectively interconnecting the antenna to a single one of the first power amplifier, the second power amplifier, and the third power amplifier.

22. The front end circuit of claim 21, further comprising:

a set of receive ports relaying signals of the first operating mode and the second operating mode received from the antenna; and

a second receive port relaying signals of the third operating mode received from the antenna.

23. The front end circuit of claim 22, further comprising:

a diplexer coupling an output of the third power amplifier and the second receive port to the antenna.

24. The front end circuit of claim 23, further comprising:

a first output switch selectively interconnecting the second power amplifier to the diplexer.

25. The front end circuit of claim 24, wherein the first output switch, the third power amplifier, and the first switch network are fabricated on a single die.

26. The front end circuit of claim 23, further comprising:

a second switch network selectively interconnecting the third amplifier to the diplexer.

27. The front end circuit of claim 26, wherein the first switch network and the second switch network are fabricated on a single die.

28. The front end circuit of claim 26, further comprising:

a third switch network selectively interconnecting the first switch network and the second switch network to the third power amplifier.

29. A switching module for interconnecting a transceiver with at least two outputs to respective amplifiers having each outputs connectible to an antenna, the switching module comprising:

a first transmit input port connectible to the transceiver;

a second transmit input port connectible to the transceiver;

a first switch network selectively interconnecting the first and second transmit input ports to a first one of the amplifiers;

a second switch network selectively interconnecting the first switch network to a second one of the amplifiers; and

a third switch network selectively interconnecting the first one of the amplifiers and the second switch network to the antenna.

30. The switching module of claim 29, wherein the amplifiers are deactivated with first, second and third switch networks being interconnected to directly transmit a signal from the transmit input ports to the antenna without any selective interconnections to the amplifiers.

31. A front end circuit for connecting an antenna to a transceiver having a GSM (Global System for Mobile Communications) operating mode, an EDGE (Enhanced Data rates for GSM Evolution) operating mode, and a CDMA operating mode, the front end circuit comprising:

a combined GSM and EDGE signals transmission port;

a CDMA signals transmission port;

a GSM amplifier circuit having non-linear operational characteristics;

a CDMA amplifier circuit having linear operational characteristics;

a switch network selectively interconnecting the combined GSM and EDGE signals transmission port to the CDMA amplifier circuit and to the GSM amplifier circuit; and

a multi-position switch interconnecting a selected single one of the GSM amplifier circuit and the CDMA amplifier circuit to the antenna.

32. The front end circuit of claim 31, further comprising:

a combined GSM and EDGE reception port interconnected to the switch network; and

a CDMA reception port interconnected to the switch network;

wherein switch network further selectively interconnects the antenna to the CDMA reception port and the combined GSM and EDGE reception port.

33. An RF switch circuit, comprising:

a combination input port receptive to first and second operating mode signals;

a single input port receptive to third operating mode signals;

a single output port for the first operating mode signals;

a combination output port for the second and third operating mode signals; and

a switching network with one or more control lines selectively connecting the combination input port to the combination output port, the single input port to the combination output port, and the combination input port to the single output port, the connections of the switching network being selectable by an activation the one or more control lines.

34. The switch circuit of claim 33, wherein the switching network includes:

a first amplifier segment connected to the combination input port and activated by a first one of the control lines; and

a second amplifier segment connected to the first amplifier segment.

35. The switch circuit of claim 34, wherein the second amplifier segment includes a first operating mode stage connected to the single output port and activated by a second one of the control lines.

36. The switch circuit of claim 35, wherein the first operating mode stage includes an output matching circuit.

37. The switch circuit of claim 34, wherein the second amplifier segment includes a second operating mode stage connected to the combination output port and activated by a third one of the control lines.

38. The switch circuit of claim 37, wherein the second operating mode stage includes an output matching circuit.

39. The switch circuit of claim 33, wherein the switching network includes:

a third amplifier segment connected to the single input port and the combination output port, the third amplifier segment being activated by a fourth one of the control lines.

40. The switch circuit of claim 39, wherein the second amplifier segment includes an output matching circuit.

41. The switch circuit of claim 33, wherein:

the first operating mode signal is a GSM signal;

the second operating mode signal is an EDGE signal; and

the third operating mode signal is a CDMA signal.

42. An active switching circuit including first and second input ports and first and second output ports, comprising:

a first amplifier segment including a first transistor with a base, a collector and an emitter, the base being connected to the first input port and a first control line;

a second amplifier segment including;

a second transistor with a base, a collector, and an emitter, the base being connected to a second control line, the collector being connected to a third control line and the first output, and the emitter being connected to the collector of the first transistor;

a third transistor with a base connected to a third control line, a collector, and an emitter connected to the emitter of the second transistor and the collector of the first transistor; and

a fourth transistor with a base connected to the collector of the third transistor, the base of the third transistor, and the third control line, a collector, and an emitter connected to the second output port; and

a third amplifier segment including a fifth transistor with a base, a collector, and an emitter, the base being connected to the first input port and a fourth control line, and the collector being connected to the second output port.

43. The switching circuit of claim 42, wherein in a first mode, the first transistor and the second transistor are activated, a signal being transmissible from the first input port to the first output port.

44. The switching circuit of claim 42, wherein in a second mode, the first transistor, the third transistor, and the fourth transistor are activated, a signal being transmissible from the first input port to the second output port

45. The switching circuit of claim 42, wherein in a third mode, the fifth transistor is activated, a signal being transmissible from the second input port to the second output port.

46. The switching circuit of claim 42, wherein the one or more of the first, second and third amplifier segments include a plurality of amplifier stages.

47. The switching circuit of claim 42, wherein the transistors have a structure selected from the group consisting of:

bipolar junction and hetero-junction bipolar.

48. The switching circuit of claim 42, wherein:

the transistors have a structure selected from the group consisting of;

metal semiconductor field effect, metal oxide semiconductor field effect, and high electron mobility;

the respective one of the collectors of the transistors corresponding to drains;

the respective one of the emitters of the transistors corresponding to sources; and

the respective one of the bases of the transistors corresponding to gates.

49. The switching circuit of claim 42, wherein the active switching circuit is fabricated on a single semiconductor die.

50. The switching circuit of claim 42, wherein the first amplifier segment includes an input matching circuit.