Memory System Having Multiple Vias at Junctions Between Traces

• US 20100277965A1
• Filed: 04/30/2009
• Published: 11/04/2010
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kono, Fumihiro
• Granted Patent: US 7,940,544 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened portion that provides sufficient overlap with the other trace to allow the two or more vias to be formed between the traces at the overlap. Parallel traces for global write lines that carry a write signal and its inverse may be positioned more than one maximum-density grid space apart to allow the widened portions to be formed between the traces. A global read line that is formed in a different metal layer from the global write line traces may be positioned in a grid space between the global write line traces to reduce the capacitance of this line.

Claims

1. An improvement to a memory system having a hierarchical bitline structure that includes a first global write line configured to carry a first global write signal and a second global write line configured to carry a second global write signal that is the inverse of the first global write signal, wherein the first global write line includes first and third traces and the second global write line includes second and fourth traces, wherein each of the first and second traces is formed in a first metal layer of an integrated circuit (IC) and each of the third and fourth traces is formed in a second metal layer of the IC which is different from the first metal layer, wherein the improvement comprises:

at least one of the first and third traces having a widened portion that has sufficient overlap with the other of the first and third traces to accommodate at least two vias;

at least two substantially adjacent vias connecting the first and third traces where the first and third traces overlap.

2. The improvement of claim 1, wherein at least one of the second and fourth traces has a widened portion that has sufficient overlap with the other of the second and fourth traces to accommodate at least two vias, and wherein at least two substantially adjacent vias connect the second and fourth traces where the second and fourth traces overlap.

3. The improvement of claim 2, wherein the first, second, third and fourth traces have a nominal width and wherein the widened portions are at least twice the nominal width.

4. The improvement of claim 3, wherein each of the widened portions comprises a bumpout that extends perpendicularly from the corresponding trace.

5. The improvement of claim 4, wherein the first and second traces are parallel to each other and are separated by more than one maximum-density grid space, wherein the bumpouts are formed in the first and second traces, wherein the bumpout of the first trace extends toward the second trace, and wherein the bumpout of the second trace extends toward the first trace.

6. The improvement of claim 1, wherein the first and second traces are parallel to each other and are separated by more than one maximum-density grid space.

7. The improvement of claim 6, wherein the first and second traces are separated by two maximum-density grid spaces.

8. The improvement of claim 7, further comprising a fifth trace configured to carry a global read signal, wherein the fifth trace is positioned between the first and second traces and is formed in a third metal layer of the IC which is different from the first and second metal layers.

9. The improvement of claim 1, wherein the first trace is connected to the gate of a first transistor that is connected between a bit line and ground, and the second trace is connected to the gate of a second transistor that is connected between the bit line and Vdd.

10. The improvement of claim 1, wherein the first and third traces have a nominal width and wherein the widened portion is at least twice the nominal width.

11. A memory system comprising:

a plurality of memory cells interconnected according to a hierarchical bitline structure;

a first global write line configured to carry a first global write signal, wherein the first global write line includes first and third traces; and

a second global write line configured to carry a second global write signal that is the inverse of the first global write signal, wherein the second global write line includes second and fourth traces;

wherein each of the first and second traces is formed in a first metal layer of an integrated circuit (IC) and each of the third and fourth traces is formed in a second metal layer of the IC which is different from the first metal layer; and

wherein at least one of the first and third traces has a widened portion that has sufficient overlap with the other of the first and third traces to accommodate at least two vias, and wherein the first global write line includes at least two substantially adjacent vias connecting the first and third traces where the first and third traces overlap.

12. The memory system of clam 11, wherein at least one of the second and fourth traces has a widened portion that has sufficient overlap with the other of the second and fourth traces to accommodate at least two vias, and wherein the second global write line includes at least two substantially adjacent vias connecting the second and fourth traces where the second and fourth traces overlap.

13. The memory system of clam 12, wherein the first, second, third and fourth traces have a nominal width and wherein the widened portions are at least twice the nominal width.

14. The memory system of clam 13, wherein each of the widened portions comprises a bumpout that extends perpendicularly from the corresponding trace.

15. The memory system of clam 14, wherein the first and second traces are parallel to each other and are separated by more than one maximum-density grid space, wherein the bumpouts are formed in the first and second traces, wherein the bumpout of the first trace extends toward the second trace, and wherein the bumpout of the second trace extends toward the first trace.

16. The memory system of clam 11, wherein the first and second traces are parallel to each other and are separated by more than one maximum-density grid space.

17. The memory system of clam 16, wherein the first and second traces are separated by two maximum-density grid spaces.

18. The memory system of clam 17, further comprising a global read line configured to carry a global read signal, wherein the global read line includes a fifth trace which is positioned between the first and second traces and is formed in a third metal layer of the IC which is different from the first and second metal layers.

19. The memory system of clam 11, wherein the first trace is connected to the gate of a first transistor that is connected between a bit line and ground, and the second trace is connected to the gate of a second transistor that is connected between the bit line and Vdd.

20. The memory system of clam 11, wherein the first and third traces have a nominal width and wherein the widened portion is at least twice the nominal width.