Semiconductor memory device

• US 20100277997A1
• Filed: 04/23/2010
• Published: 11/04/2010
• Est. Priority Date: 04/29/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hyung-Seuk
• Granted Patent: US 8,189,416 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the memory device may include a precharger configured to charge the bit line and the inverted bit line to a first voltage before a read operation, a first sense amplifier having a first transistor connected between to the bit line and a first node, the first transistor including a gate to which a signal of the inverted bit line is applied. The semiconductor memory device may have a second transistor connected between the inverted bit line and a second node, the second transistor including a gate to which a signal of the bit line is applied, and the first sense amplifier configured to amplify a voltage of the bit line or the inverted bit line to a second voltage based on to the second voltage applied to one of the first node and the second nodes during the read operation. The semiconductor memory device may also have a bias unit configured to generate a voltage difference between the first node and the second node, and a sense amplifier driver configured to apply the second voltage to one of the first and second nodes based on one of the first and second selected word lines during the read operation.

Claims

1. A semiconductor memory device, comprising:

a first memory cell connected between a first word line and a bit line;

a second memory cell connected between a second word line and an inverted bit line;

a precharger configured to charge the bit line and the inverted bit line to a first voltage before a read operation;

a first sense amplifier including a first transistor connected between the bit line and a first node, the first transistor including a gate to which a signal of the inverted bit line is applied, and the first sense amplifier including a second transistor connected between the inverted bit line and a second node, the second transistor including a gate to which a signal of the bit line is applied, and the first sense amplifier configured to amplify a voltage of one of the bit line and the inverted bit line to a second voltage based on the second voltage applied to one of the first node and the second node during the read operation;

a bias unit configured to generate a voltage difference between the first node and the second node; and

a sense amplifier driver configured to apply the second voltage to one of the first and second nodes based on the selected one of the first and second word lines during the read operation.

2. The semiconductor memory device according to claim 1, wherein the sense amplifier driver is configured to apply the second voltage to the second node if the first word line is selected during the read operation, and apply the second voltage to the first node if the second word line is selected.

3. The semiconductor memory device according to claim 1, wherein the sense amplifier driver applies the second voltage to the second node and then the first node if the first word line is selected, and applies the second voltage to the first node and then the second node if the second word line is selected.

4. The semiconductor memory device according to claim 1, further comprising:

a second sense amplifier connected between the bit line and the inverted bit line, and configured to amplify a voltage of one of the inverted bit line and the bit line to the first voltage in response to the first voltage during the read operation.

5. The semiconductor memory device according to claim 1, wherein the bias unit includes a bias transistor connected between the first node and the second node and including a gate to which a bias voltage is applied.

6. The semiconductor memory device according to claim 5, wherein the first voltage is a power supply voltage, the second voltage is a ground voltage.

7. The semiconductor memory device according to claim 6, wherein the bias transistor, the first transistor and the second transistor are n-channel metal oxide semiconductor (NMOS) transistors.

8. The semiconductor memory device according to claim 5, wherein the first voltage is a ground voltage, the second voltage is a power supply voltage.

9. The semiconductor memory device according to claim 8, wherein the bias transistor, the first transistor and the second transistor are p-channel metal oxide semiconductor (PMOS) transistors.

10. The semiconductor memory device according to claim 5, wherein there are a plurality of first sense amplifiers and bias transistors, and each of the bias transistors is connected between the first node and the second node of a corresponding one of the first sense amplifiers.

11. The semiconductor memory device according to claim 5, further comprising:

a sense amplifier region including a plurality of prechargers, first sense amplifiers and second sense amplifiers; and

a junction region in which the sense amplifier driver is disposed,

wherein the bias transistor is disposed in the sense amplifier region.

12. The semiconductor memory device according to claim 5, further comprising:

a sense amplifier region including a plurality of prechargers, first sense amplifiers and second sense amplifiers ; and

a junction region in which the sense amplifier driver is disposed,

wherein the bias transistor is disposed in the junction region.