METHODOLOGY FOR PROCESSING A PANEL DURING SEMICONDUCTOR DEVICE FABRICATION

• US 20100279467A1
• Filed: 04/29/2009
• Published: 11/04/2010
• Est. Priority Date: 04/29/2009
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Magnus, Alan J., Poarch, Justin E., Wright, Jason R.
• Granted Patent: US 7,892,950 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).

Claims

1. A method for processing a panel during the formation of semiconductor devices, said panel including a plurality of semiconductor dies interposed between first and second opposing external surfaces, wherein said first external surface is an interconnect surface, each of said plurality of semiconductor dies is in electrical communication with said interconnect surface, and said method comprises:

forming a series of grooves in said interconnect surface, said grooves extending partially through said panel so that said panel remains intact, said grooves being coincident with a dicing pattern for said panel, and said grooves having a groove width; and

following said forming operation, dicing through said panel from said interconnect surface utilizing a dice tool in accordance with said dicing pattern to singularize said plurality of semiconductor devices, said dice tool producing a dice width through said panel that is greater than said groove width, and each of said semiconductor devices including at least one of said semiconductor dies.

2. A method as claimed in claim 1 wherein said panel exhibits a thickness and said forming operation forms said grooves having a depth no greater than seventy percent of said thickness.

3. A method as claimed in claim 1 wherein said panel exhibits a thickness and said forming operation forms said grooves having a depth no less than twenty-five percent of said thickness.

4. A method as claimed in claim 1 wherein said groove width is no greater than seventy percent of said dice width.

5. A method as claimed in claim 1 wherein said dicing pattern is a two-dimensional grid array over said interconnect surface, and said forming operation forms said series of grooves in both dimensions of said two-dimensional grid array.

6. A method as claimed in claim 1 further comprising:

prior to said forming operation, mounting said panel on a support structure with said interconnect surface exposed and said second external surface in contact with said support structure; and

performing said forming and dicing operations while said panel is mounted on said support structure.

7. A method as claimed in claim 6 wherein said support structure is a tape-less support structure.

8. A method as claimed in claim 1 further comprising:

adhering said second surface of said panel to a first support structure using an adhesive material;

performing said forming operation while said panel is adhered to said first support structure;

following said forming operation, removing said panel from said first support structure;

mounting said panel on a tape-less support structure with said interconnect surface exposed and said second external surface in contact with said tape-less support structure; and

performing said dicing operation while said panel is mounted on said tape-less support structure.

9. A method as claimed in claim 1 wherein following said forming operation and prior to said dicing operation, said method further comprises:

mounting said panel on a support structure with said interconnect surface exposed and said second external surface in contact with said support structure; and

applying solder paste to said interconnect surface in accordance with a solder print pattern.

10. A method as claimed in claim 9 further comprising:

following said mounting operation, placing a stencil over said interconnect surface; and

said applying operation comprises transferring said solder paste through said stencil to said interconnect surface.

11. A method as claimed in claim 1 wherein prior to said forming operation said method further comprises:

concurrently forming an encapsulant layer overlying an inactive surface of each of said plurality of semiconductor dies to produce a panel subassembly, said encapsulant layer having an outer encapsulant surface, said outer encapsulant surface being said second external surface of said panel; and

building a substantially planar interconnect layer over an active surface of said each of said plurality of semiconductor dies to produce said panel, said active surface including device pads, said interconnect layer having an outer interconnect surface, said outer interconnect surface being said interconnect surface of said panel, said interconnect surface including external contacts interconnected with said device pads of said semiconductor dies.

12. A method for processing a panel during the formation of semiconductor devices, said panel including a plurality of semiconductor dies interposed between first and second opposing external surfaces, wherein said first external surface is an interconnect surface, each of said plurality of semiconductor dies is in electrical communication with said interconnect surface, and said method comprises:

adhering said second external surface of said panel to a first support structure using an adhesive material;

while said panel is adhered to said first support structure, forming a series of grooves in said interconnect surface, said grooves extending partially through said panel so that said panel remains intact, said grooves being coincident with a dicing pattern for said panel, and said grooves having a groove width;

following said forming operation, removing said panel from said first support structure;

mounting said panel on a second support structure with said interconnect surface exposed and said second external surface in contact with said second support structure;

applying solder paste to said interconnect surface in accordance with a solder print pattern;

following said applying operation, removing said panel from said second support structure;

mounting said panel on a tape-less support structure with said interconnect surface exposed and said second external surface in contact with said tape-less support structure; and

while said panel is mounted on said tape-less support structure, dicing through said panel from said interconnect surface utilizing a dice tool in accordance with said dicing pattern to singularize said plurality of semiconductor devices, said dice tool producing a dice width through said panel that is greater than said groove width, and each of said semiconductor devices including at least one of said semiconductor dies.

13. A method as claimed in claim 12 wherein said panel exhibits a thickness and said forming operation forms said grooves having a depth no less than twenty-five percent of said thickness.

14. A method as claimed in claim 12 wherein said dicing pattern is a two-dimensional grid array over said interconnect surface, and said forming operation forms said series of grooves in both dimensions of said two-dimensional grid array.

15. A method for processing a panel during the formation of semiconductor devices, said method comprising:

concurrently forming an encapsulant layer overlying an inactive surface of each of a plurality of semiconductor dies to produce a panel subassembly, said encapsulant layer including an outer encapsulant surface;

building a substantially planar interconnect layer over an active surface of said each of said plurality of semiconductor dies to produce said panel, said active surface including device pads, said interconnect layer including an outer interconnect surface having external contacts, said panel including said plurality of semiconductor dies interposed between said outer encapsulant surface and said outer interconnect surface, and said device pads are interconnected with said external contacts;

forming a series of grooves in said outer interconnect surface, said grooves extending partially through said panel so that said panel remains intact, said grooves being coincident with a dicing pattern for said panel, said dicing pattern being a two-dimensional grid array over said outer interconnect surface, said forming operation forms said series of grooves in both dimensions of said two-dimensional grid array; and

following said forming operation, dicing through said panel from said outer interconnect surface in accordance with said dicing pattern to singularize said semiconductor devices, each of said semiconductor devices including at least one of said semiconductor dies.

16. A method as claimed in claim 15 further comprising:

prior to said forming operation, mounting said panel on a tape-less support structure with said outer interconnect surface exposed and said outer encapsulant surface in contact with said tape-less support structure; and

performing said forming and dicing operations while said panel is mounted on said tape-less support structure.

17. A method as claimed in claim 15 further comprising:

attaching said outer encapsulant surface of said panel to a first support structure using an adhesive material;

performing said forming operation while said panel is attached to said first support structure;

following said forming operation, removing said panel from said first support structure;

mounting said panel on a tape-less support structure with said outer interconnect surface exposed and said outer encapsulant surface in contact with said tape-less support structure; and

performing said dicing operation while said panel is mounted in said tape-less support structure.

18. A method as claimed in claim 15 wherein following said forming operation and prior to said dicing operation, said method further comprises:

mounting said panel on a support structure with said outer interconnect surface exposed and said outer encapsulant surface in contact with said support structure; and

applying solder paste to said outer interconnect surface in accordance with a solder print pattern.

19. A method as claimed in claim 18 wherein said support structure is a tape-less support structure, and said method further comprises:

prior to said mounting operation, attaching said outer encapsulant surface of said panel to a second support structure using an adhesive material;

performing said forming operation while said panel is attached to said second support structure;

following said forming operation, removing said panel from said second support structure;

performing said mounting said panel on said tape-less support structure subsequent to said removing operation and prior to said applying operation; and

performing said dicing operation while said panel is mounted in said tape-less support structure subsequent to said applying operation.