METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20100279474A1
• Filed: 04/27/2010
• Published: 11/04/2010
• Est. Priority Date: 05/01/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AKIMOTO, Kengo, KAWAE, Daisuke
• Granted Patent: US 8,278,162 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming a first conductive layer over an insulating surface;

performing a first patterning to form a first gate electrode;

forming a first insulating film over the first gate electrode;

forming a second conductive layer over the first insulating film;

performing a second patterning to form a wiring layer;

forming an oxide semiconductor film, a second insulating film, and a third conductive layer over the first insulating film and the wiring layer;

performing a third patterning to form an island-shaped oxide semiconductor film, an island-shaped second insulating film over the island-shaped oxide semiconductor film, and a second gate electrode over the island-shaped second insulating film;

forming an interlayer insulating layer covering the first insulating film, the wiring layer, the island-shaped oxide semiconductor film, the island-shaped second insulating film, and the second gate electrode;

performing a fourth patterning to form an opening portion reaching the second gate electrode and an opening portion reaching the wiring layer;

forming a conductive material over the interlayer insulating layer; and

performing a fifth patterning to form a lead wiring connected to the second gate electrode and a pixel electrode connected to the wiring layer.

3. The method for manufacturing a semiconductor device according to claim 1 or claim 2,

wherein the oxide semiconductor film is a first oxide semiconductor film,

wherein a second oxide semiconductor film is formed over the wiring layer by performing the second patterning, and

wherein a buffer layer formed from the second oxide semiconductor film is provided by performing the third patterning in a region where the oxide semiconductor film and the wiring layer overlap with each other.

4. The method for manufacturing a semiconductor device according to claim 1 or claim 2,

wherein the oxide semiconductor film is a first oxide semiconductor film, and

wherein a second oxide semiconductor film is formed below the wiring layer by performing the second patterning.

5. The method for manufacturing a semiconductor device according to claim 1 or claim 2,

wherein the lead wiring is provided to overlap with the second gate electrode.

6. The method for manufacturing a semiconductor device according to claim 1 or claim 2,

wherein the interlayer insulating layer is formed using polyimide.

8. The method for manufacturing a semiconductor device according to claim 1 or claim 2,

wherein the oxide semiconductor film includes silicon oxide.

9. The method for manufacturing a semiconductor device according to claim 1 or claim 2,

wherein the lead wiring is formed to be connected to the first gate electrode.

10. The method for manufacturing a semiconductor device according to claim 1 or claim 2,

wherein the second insulating film is formed to a thickness of from 50 nm to 500 nm inclusive.

2. A method for manufacturing a semiconductor device comprising:

forming a first conductive layer over an insulating surface;

performing a first patterning to form a first gate electrode;

forming a first insulating film over the first gate electrode;

forming a second conductive layer over the first insulating film;

performing second patterning to form a wiring layer;

forming an oxide semiconductor film, a channel protective film, a second insulating film, and a third conductive layer over the first insulating film and the wiring layer;

performing a third patterning to form an island-shaped oxide semiconductor film, an island-shaped channel protective film over the island-shaped oxide semiconductor film, an island-shaped second insulating film over the island-shaped channel protective film, and a second gate electrode over the island-shaped second insulating film;

forming an interlayer insulating layer covering the first insulating film, the wiring layer, the island-shaped oxide semiconductor film, the island-shaped channel protective film, the island-shaped second insulating film, and the second gate electrode;

performing a fourth patterning to form an opening portion reaching the second gate electrode and an opening portion reaching the wiring layer;

forming a conductive material over the interlayer insulating layer; and

performing a fifth patterning to form a lead wiring connected to the second gate electrode and a pixel electrode connected to the wiring layer.

7. The method for manufacturing a semiconductor device according to claim 2,

wherein the channel protective film is formed using amorphous silicon.