Method For Releasing a Thin-Film Substrate

• US 20100279494A1
• Filed: 03/08/2010
• Published: 11/04/2010
• Est. Priority Date: 10/09/2006
• Status: Active Grant

• Current Assignee: Ob Realty, LLC
• Original Assignee: Solexel, Inc.
• Inventors: Moslehi, Mehrdad M., Kramer, Joe, Wang, David Xuan-Qi, Ricolcol, Rafael
• Granted Patent: US 8,293,558 B2
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

The present disclosure relates to methods for selectively etching a porous semiconductor layer to separate a thin-film semiconductor substrate (TFSS) having planar or three-dimensional features from a corresponding semiconductor template. The method involves forming a conformal sacrificial porous semiconductor layer on a template. Next, a conformal thin film silicon substrate is formed on top of the porous silicon layer. The middle porous silicon layer is then selectively etched to separate the TFSS and semiconductor template. The disclosed advanced etching chemistries and etching methods achieve selective etching with minimal damage to the TFSS and template.

Claims

1. A method for fabrication of a thin-film semiconductor substrate by releasing it from a semiconductor template through the use of a porous semiconductor layer, the method comprising:

forming a porous semiconductor layer on a semiconductor template, said porous semiconductor layer conformal to said semiconductor template;

forming a thin-film semiconductor substrate on said porous semiconductor layer, said thin-film semiconductor substrate conformal to said porous semiconductor layer; and

selectively etching said porous semiconductor layer with an etchant to separate said thin-film semiconductor substrate and said semiconductor template.

2. The method of claim 1, wherein said step of selectively etching said porous semiconductor layer further comprises degassing said etchant prior to said selective etching step.

3. The method of claim 1, wherein said step of selectively etching said porous semiconductor layer further comprises degassing said etchant during said selective etching step.

4. The method of claim 1, wherein said step of selectively etching said porous semiconductor layer occurs in a vacuum chamber.

5. The method of claim 1, wherein said step of selectively etching said porous semiconductor layer further comprises ultrasonically streaming said etchant at said porous semiconductor layer.

6. The method of claim 1, wherein said step of selectively etching said porous semiconductor layer further comprises megasonically streaming said etchant at said porous semiconductor layer.

7. The method of claim 1, wherein said step of selectively etching said porous semiconductor layer further comprises directing acoustic waves at said porous semiconductor layer.

8. The method of claim 7, wherein said acoustic waves comprise acoustic waves having a plurality of frequencies.

9. The method of claim 1, wherein said step of forming a porous semiconductor layer further comprises the step of forming a porous semiconductor bi-layer comprising a low porosity layer in the range of 15-30% and a high porosity layer in the range of 60-85%.

10. The method of claim 9, wherein said step of selectively etching said porous semiconductor layer further comprises mechanically delaminating said high porosity silicon layer using low frequency ultrasonic energy.

11. The method of claim 1, wherein said step of forming a porous semiconductor layer further comprises the step of forming a porous silicon layer.

12. The method of claim 11, wherein said etchant comprises a tetramethylammonium hydroxide (TMAH) solution.

13. The method of claim 11, wherein said etchant comprises a tetramethylammonium hydroxide (TMAH) and ammonium persulfate crystalline additive solution.

14. The method of claim 11, wherein said etchant comprises a potassium hydroxide (KOH) solution.

15. The method of claim 11, wherein said etchant comprises a potassium hydroxide (KOH) and hydrofluoric (HF) acid solution.

16. The method of claim 11, wherein said etchant comprises a potassium hydroxide (KOH) and isopropyl alcohol (IPA) solution.

17. The method of claim 11, wherein said etchant comprises a potassium hydroxide (KOH) and surfactant solution.

18. The method of claim 11, wherein said etchant comprises a potassium hydroxide (KOH), hydrofluoric (HF) acid, and surfactant solution.

19. The method of claim 1, wherein said step of forming a thin-film semiconductor substrate further comprises the step of forming a thin-film silicon substrate having three-dimensional features.

20. The method of claim 1, wherein said step of forming a porous semiconductor layer on a semiconductor template further comprises the step of forming a porous semiconductor layer on a silicon template having three-dimensional features.