ARCHITECTURE FOR A SELF-HEALING COMPUTER SYSTEM

• US 20100281134A1
• Filed: 03/31/2009
• Published: 11/04/2010
• Est. Priority Date: 03/31/2009
• Status: Active Grant

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Moussa, Nader W., Melen, Roger D., Ikai, Hideo, Honda, Makoto, Kato, Kozo
• Granted Patent: US 8,775,886 B2
• Time in Patent Office: Days
• US Class Current: 709/217
• CPC Class Codes: G06F 11/0739 in a data processing system embedded in automotive or aircraft systems
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

The self-healing system comprises a self-healing processor and an error mitigation system. The self-healing processor includes a code block associated with the operation of a portion of digital logic. The self-healing processor also includes a dynamic signature analysis circuit. The processor executes the code block. The dynamic signature analysis circuit creates a dynamic signature representing the operation of the portion of digital logic associated with the code block. The error mitigation system receives the dynamic signature from the dynamic signature analysis circuit. The error mitigation system compares the dynamic signature to a static signature to determine if the signatures match. If the signatures do not match, then the digital logic associated with the code block has an error. The error mitigation system retries execution of the code block. The error mitigation system stores log information describing the above events.

Claims

1. A self-healing system, the system comprising:

a processor having a code block, a dynamic signature analysis circuit and an error mitigation system,

the code block associated with the operation of a portion of digital logic and the dynamic signature analysis circuit, the processor coupled to execute the code block, the dynamic signature analysis circuit coupled to create a dynamic signature representing the operation of the portion of digital logic associated with the code block;

the error mitigation system coupled for receiving the dynamic signature from the dynamic signature analysis circuit, the error mitigation system having a static signature representing error-free execution of the code block, the error mitigation system comparing the dynamic signature to the static signature to detect an error in the digital logic based on whether the signatures match, the error mitigation system coupled to retry execution of the code block if the signatures do not match, the error mitigation system storing log information.

2. The self-healing system of claim 1 further comprising:

a network interface coupled to upload the log information to an external system.

3. The self-healing system of claim 1 further comprising:

a network interface coupled to receive update information from an external system, the update information including information for reconfiguring the code block and/or the digital logic.

4. The self-healing system of claim 1 further comprising:

an interface coupled to receive update information from a storage device, the update information including information for reconfiguring the code block and/or the digital logic.

5. The self-healing system of claim 1, wherein the log information comprises a description of a detected error, the code block for which an error was detected, a time when the error was detected, a location when the error was detected and a number of retry attempts for the detected error.

6. The self-healing system of claim 1, wherein:

the error mitigation system is coupled to receive a dynamic signature from the dynamic signature circuit for the retried execution of the code block, the error mitigation system comparing the dynamic signature for the retried execution to the static signature to determine if the signatures match, the error mitigation system continuing to retry execution of the code block until either the signatures match or a predetermined number of retries are executed.

7. The self-healing system of claim 6, wherein:

the error mitigation system includes a set of alternative configurations for the digital logic associated with the code block, the error mitigation system coupled to implement one of the alternative configurations from the set of alternative configurations, the error mitigation system retrying execution of the code block, receiving a dynamic signature for this retry execution from the dynamic signature analysis circuit, and comparing this dynamic signature to the static signature to determine if the signatures match.

8. The self-healing system of claim 7, wherein:

the error mitigation system includes a lookup table, the lookup table having a list that ranks the order in which the alternative configurations from the set of alternative configures should implemented, the error mitigation system accessing the lookup table to determine which one of the alternative configurations from the set of alternative configurations to implement.

9. The self-healing system of claim 7, wherein the alternative configurations are implemented using emulation software, a field-programmable logic array and/or a soft-core processor.

10. The self-healing system of claim 7, wherein the error mitigation system continues to implement the alternative configurations and retry execution of the code block until either the signatures match or all of the alternative configurations for the code block have been implemented.

11. The self-healing system of claim 7, wherein the log information comprises a description of the detected error, the code block for which the error was detected, a time when the error was detected, a location when the error was detected, a number of retry attempts for the detected error, the alternative configurations implemented and results for the alternative configurations.

12. A method for detecting and mitigating an error in digital logic, the method comprising:

executing a code block, the code block associated with operation of a portion of the digital logic;

creating a dynamic signature representing operation of the portion of digital logic;

comparing the dynamic signature to a static signature to detect an error in the digital logic based on whether the signatures match, the static signature representing an error-free execution of the code block;

retrying execution of the code block responsive to detecting an error; and

storing log information.

13. The method of claim 12 further comprising:

uploading the log information to a central server.

14. The method of claim 12 further comprising:

receiving update information from a central server, the update information including information for reconfiguring the code block and/or the digital logic.

15. The method of claim 12 further comprising:

receiving update information from a storage device, the update information including information for reconfiguring the code block and/or the digital logic.

16. The method of claim 12, wherein the log information comprises a description of the detected error, the code block for which the error was detected, a time when the error was detected, a location when the error was detected and a number of retry attempts for the detected error.

17. A method for detecting and mitigating an error in digital logic, the method comprising:

executing a code block, the code block associated with operation of a portion of the digital logic;

creating a dynamic signature representing operation of the portion of digital logic;

comparing the dynamic signature to a static signature to detect an error in the digital logic based on whether the signatures match, the static signature representing an error-free execution of the code block;

retrying execution of the code block;

receiving a dynamic signature for the retried execution of the code block;

comparing the dynamic signature for the retried execution to the static signature to determine if the signatures match;

continuing to retry execution of the code block until either the signatures match or a predetermined number of retries are executed; and

storing log information.

18. The method of claim 17 further comprising:

implementing an alternative configuration from a set of alternative configurations;

retrying execution of the code block to determine whether the implemented alternative configuration results in error-free operation of the code block;

receiving a dynamic signature for this retry execution from the dynamic signature analysis circuit; and

comparing this dynamic signature to the static signature to determine if the signatures match.

19. The method of claim 18 further comprising:

accessing a lookup table to determine which one of the alternative configurations from the set of alternative configurations to implement, the lookup table having a list that ranks the order in which the alternative configurations from the set of alternative configures are implemented.

20. The method of claim 18, wherein the alternative configurations are implemented using emulation software, field-programmable logic arrays and/or soft-core processors.

21. The method of claim 18, wherein the log information comprises a description of the detected error, the code blocks for which the error was detected, a time when the error was detected, a location when the error was detected, a number of retry attempts for the detected errors, the alternative configurations implemented and results for the alternative configurations.