SYSTEMS AND METHODS FOR COMMUNICATIONS

• US 20100281334A1
• Filed: 05/01/2009
• Published: 11/04/2010
• Est. Priority Date: 05/01/2009
• Status: Active Grant

• Current Assignee: Mirics Semiconductor Limited
• Original Assignee: Mirics Semiconductor Limited
• Inventors: Aydinlik, Mehmet, Budin, Dan
• Granted Patent: US 8,312,346 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/612 Aspects specific to channel or signal-to-noise ratio estimation H03M13/63 takes precedence
• CPC Class Codes: H03M 13/6337 Error control coding in combination with channel estimation
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing
• CPC Class Codes: H03M 13/6508 Flexibility, adaptability, parametrability and configurability of the implementation

Abstract

Systems, methods, and an article of manufacture for performing serial concatenated decoding are shown and described. The decoding includes monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding and determining whether applying sub-optimal inner decoding would reduce a computational load experienced by a processor performing the serial concatenated decoding when compared to the computation load experienced by the processor when optimal inner decoding is applied.

Claims

1. A method of performing serial concatenated decoding having inner decoding and outer decoding, the method comprising the steps of:

monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding;

determining, in response to the measure of the number of corrections, whether applying sub-optimal inner decoding would reduce a computational load experienced by a processor performing the serial concatenated decoding when compared to the computation load experienced by the processor when optimal inner decoding is applied; and

applying, by the processor, sub-optimal inner decoding on data being serially concatenated decoded when the determination indicates that the processing load experienced is reduced.

2. The method of claim 1 further comprising temporarily applying optimal inner decoding to a portion of the plurality of data blocks previously decoded with the sub-optimal decoding, in response to an indication that an output of the outer decoding contains an error.

3. The method of claim 1 wherein monitoring a measure of the number of corrections made to a plurality of blocks of data by the outer decoding comprises monitoring the byte error rate of an output of the inner decoding.

4. The method claim 1 wherein outer decoding comprises applying a Reed-Solomon decoding algorithm.

5. The method of claim 1 further comprising deinterleaving, prior to outer decoding, a result of the inner decoding.

6. The method of claim 1 wherein applying optimal inner decoding comprises applying a sixty-four state Viterbi decoding.

7. The method of claim 1 wherein applying sub-optimal inner decoding comprises applying a thirty-two state Viterbi decoding.

8. The method of claim 1 wherein applying optimal inner decoding comprises applying log-MAP turbo decoding algorithm.

9. The method of claim 1 wherein applying sub-optimal inner decoding comprises applying a max-log-MAP turbo decoding algorithm.

10. The method of claim 1 wherein applying sub-optimal inner decoding comprises applying a LDPC decoding having a reduced number of iterations when compared to the number of iterations of optimal LDPC inner decoding.

11. A system for serial concatenated decoding, the system comprising:

a selector having an input and a plurality of outputs;

an optimal inner decoder having an output and an input in communication with a first selector output;

a sub-optimal inner decoder having an output and an input in communication with a second selector output; and

an outer decoder in communication with the output of each of the optimal inner decoder and sub-optimal inner decoder, the outer decoder having an output in communication with the selector that determines whether the optimal inner decoder or sub-optimal inner decoder receives data for decoding based on monitoring a measure of the number of corrections made to a plurality of blocks of data during operation of the outer decoder.

12. The system of claim 11 further comprising a buffer having an output in communication

13. The system of claim 11 further comprising a deinterleaver in communication with the outputs of each of the optimal inner decoder and sub-optimal inner decoder to receive the output of the inner decoders and also in communication with the outer decoder.

14. The system of claim 11 wherein the optimal inner coder comprises a sixty-four state Viterbi decoder and the sub-optimal inner decoder comprises a thirty-two state Viterbi decoder.

15. The system of claim 11 wherein the outer decoder comprises a Reed-Solomon decoder.

16. The system of claim 11 wherein the optimal inner decoder comprises log-MAP turbo decoder and the sub-optimal inner decoder comprises a max-log-MAP turbo decoder.

17. The system of claim 11 wherein the optimal inner decoder comprises LDPC decoder and the sub-optimal inner decoder comprises an LDPC decoder that implements fewer iterations then optimal inner decoder.

18. The system of claim 11 wherein the output of the outer decoder controls whether optimal inner decoding is used to redecode at least a portion of the plurality of data blocks that were previously decoded using sub-optimal inner decoding when the output of the outer decoder contains an error.

19. An article of manufacture comprising:

a machine readable storage medium; and

executable program instructions embodied in the machine readable storage medium that when executed by a programmable system causes the system to perform functions of serial concatenated decoding having inner decoding and outer decoding, the functions comprising;

monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding;

determining, in response to the measure of the number of corrections, whether applying sub-optimal inner decoding would reduce a computational load experienced by a processor of the programmable system performing the serial concatenated decoding when compared to the computation load experienced by the processor when optimal inner decoding is applied; and

applying, by the processor, sub-optimal inner decoding on data being serially concatenated decoded when the determination indicates that the processing load experienced is reduced.

20. The article of manufacture of claim 19 wherein the functions further comprise temporarily applying optimal inner decoding to a portion of the plurality of data blocks previously decoded with the sub-optimal decoding, in response to an indication that an output of the outer decoding contains an error.

21. The article of manufacture of claim 19 wherein the function of monitoring a measure of the number of corrections made to a plurality of blocks of data by the outer decoding comprises a function of monitoring the byte error rate of an output of the inner decoding

22. The article of manufacture of claim 19 wherein the function of applying outer decoding comprises the function of applying a Reed-Solomon decoding algorithm.

23. The article of manufacture of claim 19 wherein the functions further comprise deinterleaving, prior to outer decoding, a result of the inner decoding.

24. The article of manufacture of claim 19 wherein the function of applying optimal inner decoding comprises applying a sixty-four state Viterbi decoding.

25. The article of manufacture of claim 19 wherein the function of applying sub-optimal inner decoding comprises applying a thirty-two state Viterbi decoding.

26. The article of manufacture of claim 19 wherein the function of applying optimal inner decoding comprises applying log-MAP turbo decoding algorithm.

27. The article of manufacture of claim 19 wherein the function of applying sub-optimal inner decoding comprises applying a max-log-MAP turbo decoding algorithm.

28. The article of manufacture of claim 19 wherein the function of applying sub-optimal inner decoding comprises applying a LDPC decoding having a reduced number of iterations when compared to the number of iterations of optimal LDPC inner decoding.