ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES

• US 20100281340A1
• Filed: 04/30/2009
• Published: 11/04/2010
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Franceschini, MIchele M., Lastras-Montano, Luis A., Karidis, John P., Jagmohan, Ashish
• Granted Patent: US 8,341,501 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 2212/403 Error protection encoding, e.g. using parity or ECC codes
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.

Claims

1. A method for storing data comprising:

receiving write data and a write address;

applying a compression algorithm to the write data to generate compressed data;

applying an endurance code to the compressed data, the endurance code selected and applied in response to the amount of space saved by applying the compression to the write data, the applying an endurance code resulting in a codeword; and

writing the codeword to the write address.

2. The method of claim 1, further comprising adding error code correction (ECC) bits to the codeword before writing the codeword.

3. The method of claim 2, wherein the number of ECC bits added to the codeword is responsive to the amount of space saved by applying the compression to the write data.

4. The method of claim 2, wherein the number of ECC bits added to the codeword include a default number of ECC bits and a variable number of ECC bits responsive to the amount of space saved by applying the compression to the write data.

5. The method of claim 2, wherein the location of the ECC bits in the codeword varies.

6. The method of claim 2, wherein the writing is programmed such that at least one of a writing speed is increased, a power level is decreased, and a wear level is decreased when writing the codeword to the write address, the programming responsive to the number of ECC bits added to the codeword.

7. The method of claim 1, further comprising generating metadata for the write address, the metadata utilized by a read operation to decode the codeword written to the write address.

8. The method of claim 7, further comprising storing the metadata in a table.

9. The method of claim 1, further comprising:

reading the codeword;

performing an analysis of the codeword;

identifying the endurance code in response to the analysis;

decoding the codeword using a decoder for the identified endurance code; and

decompressing the decoded codeword to generate the write data.

10. The method of claim 1, wherein applying the compression and applying the endurance coding are performed jointly using a single encoding function.

11. A system comprising:

a receiver receiving write data and a write address;

a data compressor applying a compression algorithm to the write data to generate compressed data;

an endurance coder applying an endurance code to the compressed data, the endurance code selected and applied in response to the amount of space saved by applying the compression to the write data, the applying an endurance code resulting in a codeword; and

a memory writer writing the codeword to the write address.

12. The system of claim 11, further comprising an error correction encoder adding error code correction (ECC) bits to the codeword before the codeword is written by the memory writer.

13. The system of claim 12 wherein the location of the ECC bits in the codeword varies.

14. A method for accessing memory, the method comprising:

retrieving a codeword from a memory address;

multiplying the codeword by a metadata matrix to recover metadata for the codeword, the metadata including a data location specification;

identifying data in the codeword in response to the metadata; and

outputting the data as read data.

15. The method of claim 14, wherein the codeword further includes ECC bits and the method further comprises applying an ECC decoder to the codeword before performing the multiplying, the ECC decoder designed to implement an ECC code specified by a parity matrix that corresponds to the number of ECC bits in the codeword.

16. The method of claim 15, wherein the number of ECC bits in the codeword is variable.

17. The method of claim 14, wherein the codeword further includes a variable and unknown number of ECC bits and the method further comprises applying one or more ECC decoders to the codeword to locate an ECC decoder that corresponds to the number of ECC bits in the codeword.

18. The method of claim 14, further comprising:

generating the codeword, the generating comprising;

receiving the data and the metadata; and

placing the data in the codeword according to the data location specification in the metadata and such that the metadata matrix times the codeword is equal to the metadata; and

writing the codeword to the memory address.

19. A system comprising:

a memory reader retrieving a codeword from a memory address;

a metadata computer multiplying the codeword by a metadata matrix to recover metadata for the codeword, the metadata including a data location specification;

a metadata interpreter identifying data in the codeword in response to the metadata; and

a transmitter outputting the data as read data.

20. The system of claim 19, wherein the codeword further includes ECC bits and the system further comprises an ECC decoder applying an ECC code to the codeword before performing the multiplying, the ECC code designed to implement an ECC code specified by a parity matrix that corresponds to the number of ECC bits in the codeword.