MEMORY CONTROLLER AND MEMORY SYSTEM

• US 20100281342A1
• Filed: 04/27/2010
• Published: 11/04/2010
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHANG, Woo tae, YIM, Yong tae
• Granted Patent: US 8,522,114 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.

Claims

1. A memory system comprising:

a nonvolatile memory including a memory cell array and a read/write circuit configured to retrieve read data stored in the memory cell array during a read operation; and

a controller configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data,

wherein upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error, and after correcting the detected error in the received portion of the read data, resume transmission of the read data from the nonvolatile memory.

2. The memory system of claim 1, wherein the read/write circuit is configured to retrieve the read data on a first unit basis, the controller performs the error detection operation on the received portion of the read data on a second unit basis, and the first unit is larger than the second unit.

3. The memory system of claim 2, wherein the received portion of the read data includes at least one second unit sized block of the read data.

4. The memory system of claim 2, wherein the controller is further configured to receive data corresponding to a detected error of the received portion of the read data on a third unit basis, the second unit being larger than the third unit, and correct the detected error in the received data corresponding to the detected error.

5. The memory system of claim 4, wherein the controller is further configured to generate error-corrected read data following correction of the detected error and provide the error-corrected read data to the read/write circuit on the third unit basis.

6. The memory system of claim 5, wherein the controller is further configured to receive complete read data following resumption of transmission of the read data, and upon receipt of the complete read data the controller is configured to perform a copy-back operation in the nonvolatile memory.

7. The memory system of claim 2, wherein the controller comprises:

an error correction block configured to detect whether the received portion of the read data contains an error and activating a wait signal upon detecting an error in the received portion of the data; and

a state machine configured to halt the transmission of read data in response to the wait signal.

8. The memory system of claim 7, wherein,

the error correction block is further configured upon detecting an error in the received portion of the data to provide error position information related to the detected error to the state machine;

and

the state machine is further configured to correct the detected error using the error position information.

9. The memory system of claim 8, wherein the state machine is further configured following correction of the detected error to transmit a return control signal to the error correction block indicating correction of the detected error.

10. The memory system of claim 9, wherein the detected error includes a number of detected errors, and

the error correction block is further configured to count a number of return control signal transmissions, and indicate when the counted number of return control signal transmissions is equal to the number of detected errors.

11. The memory system of claim 1, wherein the nonvolatile memory and the controller are implemented to form a solid state drive (SSD).

12. A memory system comprising:

a nonvolatile memory including a memory cell array and a read/write circuit configured to retrieve read data stored on a page basis in the memory cell array during a read operation, wherein the page of read data comprises a plurality of N segments and a corresponding plurality of N parities respectively derived from the plurality of N segments; and

a controller configured to receive the page of read data from the nonvolatile memory as transmitted on a segment by segment basis, and perform an error detection and correction operation on the read data on the segment by segment basis for each one of the plurality of N segments,

wherein upon detecting an error in an Mth segment of the plurality of N segments of the read data, where M is less than N, the controller is further configured to halt further transmission of the remaining N-M segments of the read data from the nonvolatile memory, perform the error detection and correction operation on the Mth segment to correct the detected error, and after correcting the detected error in the Mth segment, resume transmission of the page of read data from the nonvolatile memory.

13. The memory system of claim 12, wherein the controller is further configured to receive data corresponding to the detected error of the Mth segment on a predetermined unit basis, a size of the predetermined unit is less than a segment of the N segments, and correcting the detected error in the received data corresponding to the detected error.

14. The memory system of claim 13, wherein the controller is further configured to generate an error-corrected data following correction of the detected error and provide the error-corrected data to the read/write circuit.

15. The memory system of claim 14, wherein the controller is further configured to receive remaining ones of the plurality of N segments following resumption of transmission of the read data, and upon receipt of all of the plurality of N segments the controller is configured to perform a copy-back operation in the nonvolatile memory.

16. The memory system of claim 12, wherein the controller comprises:

an error correction block configured to detect whether the Mth segment of the read data contains an error and activating a wait signal upon detecting an error in the Mth segment; and

a state machine configured to halt the transmission of the read data in response to the wait signal.

17. The memory system of claim 16, wherein,

the error correction block is further configured upon detecting an error in the Mth segment to provide error position information related to the detected error to the state machine;

and

the state machine is further configured to correct the detected error using the error position information.

18. The memory system of claim 17, wherein the state machine is further configured following correction of the detected error to transmit a return control signal to the error correction block indicating correction of the detected error.

19. The memory system of claim 18, wherein the detected error includes a number of detected errors, and

the error correction block is further configured to count a number of return control signal transmissions, and indicate when the counted number of return control signal transmissions is equal to the number of detected errors.

20. A method for operating a memory system including a controller and a nonvolatile memory device, the method comprising:

halting a data reading from the nonvolatile memory device when an error is detected;

correcting the detected error; and

resuming the data reading after the detected error is corrected,

wherein the data reading is performed on a first unit basis sequentially, and the detected error is corrected by randomly accessing the nonvolatile memory device on a second unit basis less than the first unit.