OXIDE SEMICONDUCTOR DEVICE INCLUDING INSULATING LAYER AND DISPLAY APPARATUS USING THE SAME

• US 20100283049A1
• Filed: 11/27/2008
• Published: 11/11/2010
• Est. Priority Date: 12/04/2007
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Watanabe, Tomohiro, Yabuta, Hisato, Sato, Ayumu, Hayashi, Ryo
• Granted Patent: US 8,502,217 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided is an oxide semiconductor device including an oxide semiconductor layer and an insulating layer coming into contact with the oxide semiconductor layer in which the insulating layer includes: a first insulating layer coming into contact with an oxide semiconductor, having a thickness of 50 nm or more, and including an oxide containing Si and O; a second insulating layer coming into contact with the first insulating layer, having a thickness of 50 nm or more, and including a nitride containing Si and N; and a third insulating layer coming into contact with the second insulating layer, the first insulating layer and the second insulating layer having hydrogen contents of 4×10²¹ atoms/cm³ or less, and the third insulating layer having a hydrogen content of more than 4×10²¹ atoms/cm³.

Claims

1. An oxide semiconductor device, comprising:

an oxide semiconductor layer; and

an insulating layer which comes into contact with the oxide semiconductor layer, wherein;

the insulating layer comprises;

a first insulating layer coming into contact with an oxide semiconductor, having a thickness of 50 nm or more, and comprising an oxide containing Si and O;

a second insulating layer coming into contact with the first insulating layer, having a thickness of 50 nm or more, and comprising a nitride containing Si and N; and

a third insulating layer coming into contact with the second insulating layer; and

the first insulating layer and the second insulating layer have hydrogen contents of 4×

10²¹ atoms/cm³ or less, and the third insulating layer has a hydrogen content of more than 4×

10²¹ atoms/cm³.

2. The oxide semiconductor device according to claim 1, wherein the first insulating layer comprises SiO_x, the second insulating layer comprises SiN_y, and the third insulating layer comprises one of SiN_z and SiO_mN_n.

3. The oxide semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are continuously formed to be an insulating layer.

4. The oxide semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises an amorphous oxide semiconductor containing at least one element selected from the group consisting of Sn, In, and Zn.

5. The oxide semiconductor device according to claim 1, wherein at least a part of the first insulating layer, the second insulating layer, and the third insulating layer is used as a gate insulating layer.

6. A display apparatus comprising:

a display device comprising an electrode; and

a field effect transistor comprising a source electrode and a drain electrode,

one of the source electrode and the drain electrode of the field effect transistor being connected to the electrode of the display device on a substrate,

wherein the field effect transistor comprises the oxide semiconductor device according to claim 1.

7. The display apparatus according to claim 6, wherein the display device comprises an electroluminescence device.

8. The display apparatus according to claim 6, wherein the display device comprises a liquid crystal cell.

9. The display apparatus according to claim 6, wherein a plurality of the display devices and a plurality of the field effect transistors are two-dimensionally arranged on the substrate.