NONVOLATILE MEMORY ARRAY COMPRISING SILICON-BASED DIODES FABRICATED AT LOW TEMPERATURE

• US 20100283053A1
• Filed: 05/11/2009
• Published: 11/11/2010
• Est. Priority Date: 05/11/2009
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Clark, Mark H., Herner, S. Brad
• Application Number:
  US12/463,530
• Publication Number:
  US 20100283053A1
• Time in Patent Office: Days
• US Class Current: 257/49
• CPC Class Codes: H10B 20/10 ROM devices comprising bipolar components
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays

Abstract

In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described.

Claims

1. A method of forming a monolithic three-dimensional memory array, the method comprising:

forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper; and

forming a silicon diode in each memory cell using a hot wire chemical vapor deposition technique, wherein the silicon diode is formed at temperatures compatible with the conductors.

3. The method of claim 1, wherein forming the silicon diode comprises forming the silicon diode using a hot wire chemical vapor deposition technique at processing temperatures below about 400°

C.

4. The method of claim 3, wherein forming the silicon diode comprises forming the silicon diode using a hot wire chemical vapor deposition technique at processing temperatures below about 250°

C.

6. The method of claim 1, wherein forming the silicon diode comprises forming a polycrystalline silicon diode.

7. The method of claim 1, wherein forming the first memory layer further comprises forming a memory element coupled to the silicon diode.

8. The method of claim 7, wherein the memory element comprises a dielectric rupture antifuse.

9. The method of claim 7, wherein the memory element comprises a reversible resistance switching element.

10. A monolithic three-dimensional memory array formed using the method of claim 1.

2. (canceled)

5. (canceled)

11. A monolithic three-dimensional memory array comprising:

a first conductor comprising copper or aluminum;

a polycrystalline silicon element coupled to the first conductor; and

a second conductor coupled to the polycrystalline silicon element, the second conductor comprising copper or aluminum.

12. The memory array of claim 11, wherein the polycrystalline silicon element comprises a diode.

13. The memory array of claim 12, wherein the polycrystalline silicon element comprises a p-i-n diode.

14. The memory array of claim 11, further comprising a memory element coupled to the polycrystalline silicon element.

15. The memory array of claim 14, wherein the memory element comprises a dielectric rupture antifuse.

16. The memory array of claim 14, wherein the memory element comprises a reversible resistance switching element.

17. A method of forming a memory cell, comprising:

forming a conductor of copper or aluminum; and

using a hot wire chemical vapor deposition technique to form a polycrystalline silicon element coupled to the conductor.

18. The method of claim 17, wherein the polycrystalline silicon element comprises a polysilicon diode.

19. The method of claim 18, wherein the polycrystalline silicon element comprises a polysilicon p-i-n diode.

20. The method of claim 17, further comprising forming a memory element coupled to the polycrystalline silicon element.

21. The method of claim 20, wherein the memory element comprises a dielectric rupture antifuse.

22. The method of claim 20, wherein the memory element comprises a reversible resistance switching element.

23. The method of claim 17, comprising using a hot wire chemical vapor deposition method at processing temperatures below about 400°

C.

24. The method of claim 23, comprising using a hot wire chemical vapor deposition method at processing temperatures below about 250°

C.

25. A memory cell formed using the method of claim 17.