Massively Parallel Interconnect Fabric for Complex Semiconductor Devices
First Claim
1. An article of manufacture comprising:
- a programmable semiconductor die substrate; and
a context die substrate;
said programmable semiconductor die substrate comprises multiple logic blocks;
said context die substrate is flipped on said programmable semiconductor die substrate;
said multiple logic blocks of said programmable semiconductor die substrate are electrically connected at transistor or gate level, with wirebondless and bumpless electrical connections, via said context die substrate, through pads of a multiple parallel interconnect fabric;
said context die substrate customizes an application for said multiple logic blocks via electrical connection through pads of said multiple parallel interconnect fabric.
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Abstract
An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.
72 Citations
20 Claims
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1. An article of manufacture comprising:
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a programmable semiconductor die substrate; and a context die substrate; said programmable semiconductor die substrate comprises multiple logic blocks; said context die substrate is flipped on said programmable semiconductor die substrate; said multiple logic blocks of said programmable semiconductor die substrate are electrically connected at transistor or gate level, with wirebondless and bumpless electrical connections, via said context die substrate, through pads of a multiple parallel interconnect fabric; said context die substrate customizes an application for said multiple logic blocks via electrical connection through pads of said multiple parallel interconnect fabric. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification