Structure and Method to Form EDRAM on SOI Substrate

• US 20100283093A1
• Filed: 05/07/2009
• Published: 11/11/2010
• Est. Priority Date: 05/07/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Byeong Y., Ho, Herbert L., Cheng, Kangguo, Iyer, Subramanian S., Pei, Chengwen, Zhu, Huilong, Wang, Geng
• Granted Patent: US 8,188,528 B2
• Time in Patent Office: Days
• US Class Current: 257/303
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

Claims

1. A memory device comprising:

at least one trench capacitor located in a semiconductor substrate, the at least one trench capacitor comprising an outer electrode provided by a doped portion of the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode;

at least one semiconductor device positioned centrally over the at least one trench capacitor, wherein the at least one semiconductor device comprises a source region, a drain region, and a gate structure, wherein the at least one semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer;

a first contact extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate; and

a second contact from the drain region of the semiconductor device into electrical contact with the conductive fill material of the at least one trench capacitor.

2. The semiconductor device of claim 1, wherein the at least one semiconductor device is a planar device.

3. The semiconductor device of claim 1, wherein the at least one semiconductor device is an n-channel field effect transistor (n-FET) or is a p-channel field effect transistor (p-FET).

4. The semiconductor device of claim 1, wherein the semiconductor substrate is a silicon containing substrate doped to an n⁺ conductivity or a p⁺ conductivity.

5. The semiconductor device of claim 1, wherein the semiconductor substrate comprises a silicon containing material doped with antimony, arsenic or phosphorous present in a concentration ranging from 2×

10¹⁸ atom/cm³ to 5×

10¹⁹ atom/cm³.

6. The semiconductor device of claim 1, wherein the node dielectric layer is comprised of a high-k dielectric material.

7. The semiconductor device of claim 1, wherein the conductive fill material comprises n⁺ polysilicon or an elemental metal.

8. The semiconductor device of claim 1, wherein each of the at least one trench capacitor is present in a trench having a width ranging from 30 nm to 300 nm and a depth ranging from 2000 nm to 6000 nm.

9. A device comprising:

a first memory device comprising a first trench capacitor having a first trench of a first width, the first trench capacitor comprising a first outer electrode provided by a first doped portion of a semiconductor substrate, a first inner electrode provided by a first conductive fill material present within the first trench, and a first node dielectric layer located between the outer electrode and the inner electrode, the first memory device further including at least one first semiconductor device located over the first trench capacitor and being separated from the first trench capacitor by a dielectric layer, wherein the first semiconductor device in electrical contact with the first trench capacitor through a first electrical contact extending from a drain of the first semiconductor device through the dielectric layer to the first inner electrode of the first trench capacitor; and

a second memory device comprising a second trench capacitor having a second trench of a second width, the second trench capacitor comprising a second outer electrode provided by a second doped portion of the semiconductor substrate, a second inner electrode provided by a second conductive fill material, and a second node dielectric layer located between the second outer electrode and the second inner electrode, the second memory device further including a second semiconductor device located over the second trench capacitor and being separated from the second trench capacitor by the dielectric layer, the second semiconductor device in electrical contact with the second trench capacitor through a second electrical contact extending from a drain of the second semiconductor device through the dielectric layer to the second inner electrode of the second trench capacitor, wherein the second width of the second trench is greater than the first width of the first trench.

10. The device of claim 9, further comprising at least one contact to the semiconductor substrate.

11. The device of claim 9, wherein the first semiconductor device is positioned centrally over the first trench capacitor, and the second semiconductor device is positioned centrally over the second trench capacitor.

12. The device of claim 9, wherein the first width ranges from 30 nm to 180 nm, and the second width ranges from 150 nm to 500 nm.

13. A method for forming a memory device comprising:

providing a semiconductor substrate;

forming a trench capacitor in the semiconductor substrate, the trench capacitor including an inner electrode comprised of a conductive fill material within a trench;

forming a first stud in the buried dielectric layer in electrical communication with the conductive material that is present within the trench and a second stud in the buried dielectric layer in electrical communication with the semiconductor substrate;

forming a semiconductor layer on the buried dielectric layer; and

forming a semiconductor device atop the semiconductor layer centrally over the trench, the semiconductor device comprising a gate structure, a source region and a drain region, wherein the drain region is in electrical communication with the first stud.

14. The method of claim 13, wherein forming the trench that contains the trench capacitor comprises forming a pad stack atop the semiconductor substrate including a first pad dielectric layer on the semiconductor substrate and a second pad dielectric layer on the first pad dielectric layer;

forming a photoresist mask atop the pad stack;

etching the pad stack selective to the photoresist mask; and

etching the semiconductor substrate to provide the trench using a remaining portion of the pad stack as an etch mask.

15. The method of claim 14, further comprising forming a node dielectric on the sidewall of the trench prior to forming the inner electrode of the trench capacitor.

16. The method of claim 13, wherein the forming of the conductive material within the trench includes chemical vapor deposition or physical deposition of the conductive material within the trench followed by planarization.

17. The method of claim 13, wherein at least one of the buried dielectric layer and the semiconductor layer are formed by deposition or layer transfer.

18. The method of claim 13, wherein the forming of the semiconductor device atop the semiconductor layer comprises forming a gate dielectric and a gate conductor of the gate structure followed by ion implantation of a p-type or n-type dopant to provide the source region and the drain region of the semiconductor device.

19. A method for forming a memory device comprising:

providing a semiconductor substrate having at least one trench capacitor formed therein;

forming a buried dielectric layer on the semiconductor substrate;

forming a semiconductor device atop the buried dielectric layer comprising a gate structure, a source region and a drain region; and

forming a first contact through the buried dielectric layer in electrical contact with the semiconductor substrate and a second contact from the drain region of the semiconductor device into electrical contact to an inner electrode of the at least one trench capacitor.

20. The method of claim 19, wherein at least one of the first contact and the second contact comprises a metal.