Nickel-Based Bonding of Semiconductor Wafers

• US 20100283138A1
• Filed: 05/06/2009
• Published: 11/11/2010
• Est. Priority Date: 05/06/2009
• Status: Abandoned Application

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Yang, Kuang L., Chen, Li
• Application Number:
  US12/436,569
• Publication Number:
  US 20100283138A1
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts

Abstract

A nickel-based material is used on one or both wafers to be bonded, and the two wafers are bonded at low temperature and pressure through interdiffusion of the nickel-based material with either another nickel-based material or aluminum. In various embodiments, nickel-based walls are formed on one wafer, and corresponding walls are formed on the other wafer from a nickel-based material or aluminum. The walls of the two wafers are placed in contact with one another under sufficient pressure and temperature to cause bonding of the walls through interdiffusion.

Claims

1. Bonded wafers comprising:

a first wafer including an array of semiconductor dies, each semiconductor die including a microelectronic device;

a second wafer; and

a configuration of walls forming a bond between the first wafer and the second wafer, wherein each wall comprises an interdiffusion of a first nickel-based material on one wafer with one of a second nickel-based material and aluminum on the other wafer.

2. The bonded wafers of claim 1, wherein the wall comprises an interdiffusion of nickel on one wafer with aluminum on the other wafer.

3. The bonded wafers of claim 2, wherein the wall comprises an interdiffusion of aluminum on the first wafer and nickel on the second wafer.

4. The bonded wafers of claim 1, wherein the wall comprises an interdiffusion of the same or different nickel-based materials on both wafers.

5. The bonded wafers of claim 1, wherein the walls are configured to hermetically seal each of the microelectronic devices in a respective cavity.

6. The bonded wafers of claim 1, wherein at least one of:

the walls hold the first wafer and second wafer at least 2 microns apart;

the walls have a wall width of between 3 and 90 microns;

the second wafer includes an array of semiconductor dies, each semiconductor die including a microelectronic device;

at least one of the wafers includes electronic circuitry; and

the microelectronic devices are MEMS devices.

7. A MEMS device comprising:

a device die including a microelectronic device;

a cap die; and

a wall bonded between the device die and the cap die and at least partially surrounding an area occupied by the microelectronic device, the wall comprising an interdiffusion of a first nickel-based material on one die with one of a second nickel-based material and aluminum on the other die.

8. The MEMS device of claim 7, wherein the wall comprises an interdiffusion of nickel on one die with aluminum on the other die.

9. The MEMS device of claim 8, wherein the wall comprises an interdiffusion of aluminum on the device die and nickel on the cap die.

10. The MEMS device of claim 7, wherein the wall comprises an interdiffusion of the same or different nickel-based materials on both dies.

11. The MEMS device of claim 7, wherein the wall is configured to hermetically seal the microelectronic device in a cavity.

12. The MEMS device of claim 7, wherein at least one of:

the wall holds the device die and the cap die at least 2 microns apart;

the walls have a wall width of between 3 and 90 microns;

the cap die includes a microelectronic device;

at least one of the dies includes electronic circuitry; and

the microelectronic device is a MEMS device.

13. A method of making semiconductor devices comprising:

depositing a nickel-based material to form a nickel-based layer on a first semiconductor wafer;

patterning the nickel-based layer to form a first configuration of nickel-based walls on the first semiconductor wafer;

depositing one of a nickel-based material and aluminum to form a material layer on a second semiconductor wafer;

patterning the material layer to form a configuration of material walls on the second semiconductor wafer;

placing the second wafer on the first wafer so that the configuration of nickel-based walls on the first wafer aligns with the configuration of walls on the second wafer;

heating the first and second wafers;

compressing the first and second wafers against each other to form a bond between the walls on the first wafer and their respective walls on the second wafer through interdiffusion; and

singulating the first and second wafers into individual semiconductor devices, each having bonded wall.

14. The method of claim 13, wherein patterning comprises etching.

15. The method of claim 13, wherein heating is performed at a temperature less than 500°

C.

16. The method of claim 15, wherein compressing applies a force between around 9 and 18 KN.

17. The method of claim 13, wherein the nickel-based walls are nickel walls and wherein the material walls are aluminum walls.

18. The method of claim 13, wherein the nickel-based walls and the material walls include the same or different nickel-based materials.

19. The method of claim 13, wherein at least one of the wafers includes an array of semiconductor dies, each semiconductor die including a microelectronic device, and wherein the walls are configured to hermetically seal each of the microelectronic devices in a respective cavity.

20. The method of claim 13, wherein at least one of:

the walls hold the first wafer and second wafer at least 2 microns apart;

the walls have a wall width of between 3 and 90 microns; and

at least one of the wafers includes electronic circuitry.