NANO-ENCAPSULATED MAGNETIC PARTICLE COMPOSITE LAYERS FOR INTEGRATED SILICON VOLTAGE REGULATORS

• US 20100283570A1
• Filed: 11/14/2007
• Published: 11/11/2010
• Est. Priority Date: 11/14/2007
• Status: Abandoned Application

• Current Assignee: Adrien R. Lavoie, Arnel M. Fajardo
• Original Assignee: Adrien R. Lavoie, Arnel M. Fajardo
• Inventors: Fajardo, Arnel M., Lavoie, Adrien R.
• Application Number:
  US11/940,142
• Publication Number:
  US 20100283570A1
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: H01F 1/0054 Coated nanoparticles, e.g. nanoparticles coated with organic surfactant
• CPC Class Codes: H01F 1/0063 in a non-magnetic matrix, e.g. granular solids granular films H01F10/007
• CPC Class Codes: H01F 1/24 the particles being insulated
• CPC Class Codes: H01F 1/26 by macromolecular organic substances
• CPC Class Codes: H01F 1/28 dispersed or suspended in a bonding agent
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0066 with a magnetic layer
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A method of forming an integrated silicon voltage regulator (ISVR) comprises providing a nano-encapsulated magnetic particle (NEMP) suspension, depositing a first layer of the NEMP suspension on an integrated circuit (IC) device, curing the first layer of the NEMP suspension to form a first NEMP composite layer, forming at least one inductor wire on the NEMP composite layer, depositing an interlayer dielectric material over the inductor wire, depositing a second layer of the NEMP suspension on the interlayer dielectric material, and curing the second layer of the NEMP suspension to form a second NEMP composite layer.

Claims

1. A method of forming an integrated silicon voltage regulator (ISVR) comprising:

providing a nano-encapsulated magnetic particle (NEMP) suspension;

depositing a first layer of the NEMP suspension on an integrated circuit (IC) device;

curing the first layer of the NEMP suspension to form a first NEMP composite layer;

forming at least one inductor wire on the NEMP composite layer;

depositing an interlayer dielectric material over the inductor wire;

depositing a second layer of the NEMP suspension on the interlayer dielectric material; and

curing the second layer of the NEMP suspension to form a second NEMP composite layer.

2. The method of claim 1, wherein the providing of the NEMP suspension comprises:

combining nano-encapsulated magnetic particles and a dielectric material.

3. The method of claim 2, wherein the dielectric material comprises methylsilsequioxane (MSSQ).

4. The method of claim 2, wherein the nano-encapsulated magnetic particles comprise magnetic particles selected from the group consisting of cobalt, nickel, and iron and a nano-encapsulation shell selected from the group consisting of aluminum oxide, silicon dioxide, silicon nitride, tantalum nitride, titanium nitride, fluorinated silicon dioxide, carbon doped oxide, TEOS, BPSG, FSG, SOG, a low-k material, a high-k material, an organic polymer, perfluorocyclobutane, polytetrafluoroethylene, an inorganic polymer, an organosilicate, silsesquioxane, siloxane, and organosilicate glass.

5. The method of claim 1, wherein the depositing of the first and second layers of the NEMP suspension comprises using a spin-coat deposition process.

6. The method of claim 5, wherein the spin-coat deposition further comprises at least one of diluting the NEMP suspension, adding a reflow agent to the NEMP suspension, and planarizing the NEMP suspension.

7. The method of claim 1, wherein the curing of the NEMP suspension comprises exposing the NEMP suspension to ultraviolet radiation or thermally annealing the NEMP suspension.

8. The method of claim 1, further comprising etching the first NEMP composite layer to form a first magnetic core material layer for the integrated silicon voltage regulator.

9. The method of claim 1, further comprising etching the second NEMP composite layer to form a second magnetic core material layer for the integrated silicon voltage regulator.

10. A method of forming an integrated silicon voltage regulator (ISVR) comprising:

depositing a first layer of photoresist material on an IC device;

patterning the first layer of photoresist material to form a first opening that exposes a potion of the IC device where the ISVR is to be formed;

providing a nano-encapsulated magnetic particle (NEMP) suspension;

depositing a first layer of the NEMP suspension in the first opening;

curing the first layer of the NEMP suspension to form a first NEMP composite layer;

forming at least one inductor wire on the NEMP composite layer;

depositing an interlayer dielectric material over the inductor wire;

depositing a second layer of photoresist material on the interlayer dielectric material;

patterning the second layer of photoresist material to form a second opening that exposes a potion of the interlayer dielectric over the inductor wire;

depositing a second layer of the NEMP suspension in the second opening; and

curing the second layer of the NEMP suspension to form a second NEMP composite layer.

11. The method of claim 10, wherein the dielectric material comprises methylsilsequioxane (MSSQ).

12. The method of claim 10, wherein the nano-encapsulated magnetic particles comprise magnetic particles selected from the group consisting of cobalt, nickel, and iron and a nano-encapsulation shell selected from the group consisting of aluminum oxide, silicon dioxide, silicon nitride, tantalum nitride, titanium nitride, fluorinated silicon dioxide, carbon doped oxide, TEOS, BPSG, FSG, SOG, a low-k material, a high-k material, an organic polymer, perfluorocyclobutane, polytetrafluoroethylene, an inorganic polymer, an organosilicate, silsesquioxane, siloxane, and organosilicate glass.

13. An apparatus comprising:

a first NEMP composite layer formed on an IC device;

an inductor wire formed on the first NEMP composite layer;

an interlayer dielectric material formed over the inductor wire; and

a second NEMP composite layer formed on the interlayer dielectric material.

14. The apparatus of claim 13, wherein the first and second NEMP composite layers comprise a plurality of nano-encapsulated magnetic particles dispersed throughout a cured dielectric material.

15. The apparatus of claim 14, wherein the magnetic particles are chosen from the group consisting of cobalt, nickel, and iron, wherein a nano-encapsulation shell on the magnetic particles is selected from the group consisting of aluminum oxide, silicon dioxide, silicon nitride, tantalum nitride, titanium nitride, fluorinated silicon dioxide, carbon doped oxide, TEOS, BPSG, FSG, SOG, a low-k material, a high-k material, an organic polymer, perfluorocyclobutane, polytetrafluoroethylene, an inorganic polymer, an organosilicate, silsesquioxane, siloxane, and organosilicate glass, and wherein the cured dielectric material comprises MSSQ.