System and method to provide transient overvoltage suppression

• US 20100284114A1
• Filed: 05/08/2009
• Published: 11/11/2010
• Est. Priority Date: 05/08/2009
• Status: Active Grant

• Current Assignee: Hamilton Sundstrand Corporation (Rtx Corporation)
• Original Assignee: Hamilton Sundstrand Corporation (Rtx Corporation)
• Inventors: Arthur, Scott D., Kilroy, Donald G.
• Granted Patent: US 8,203,815 B2
• Time in Patent Office: Days
• US Class Current: 361/86
• CPC Class Codes: H02H 3/044 Checking correct functioning of protective arrangements, e.g. by simulating a fault for differential current circuit breakers H02H3/335
• CPC Class Codes: H02H 3/202 for dc systems

Abstract

Transient overvoltage suppression circuit prevents voltage surges from damaging an attached load. The suppression circuit includes a transistor connected in series with a low-side or return line of the load. A control circuit monitors the voltage on the input line (i.e., high-side) and in response to a detected voltage transient turns the transistor OFF to isolate the load from the transient voltage.

Claims

1. A transient overvoltage protection circuit for providing transient overvoltage protection, the transient overvoltage protection circuit comprising:

a high-side input for connection to a positive terminal of an external power source;

a high-side output for connection to a positive terminal of a load;

a low-side input for connection to a negative terminal of the external power source;

a low-side output for connection to a negative terminal of the load;

a transistor connected in series between the low-side input and the low-side output; and

a control circuit connected to monitor voltage at the high-side input and in response to a detected overvoltage transient turns the transistor OFF.

2. The transient overvoltage protection circuit of claim 1, wherein the transistor is an N-channel field effect transistor (FET).

3. The transient overvoltage protection circuit of claim 1, further including:

a capacitor connected between the high-side output and the low-side output in parallel with the load.

4. The transient overvoltage protection circuit of claim 1, further including:

a test circuit connected to provide a test signal to the control circuit to simulate a transient overvoltage condition.

5. The transient overvoltage protection circuit of claim 1, wherein the control circuit includes:

a voltage divider network connected between the high-side input and the low-side input for providing a divided voltage that is a function of voltage between the high-side input and the low-side input; and

a comparator connected to compare the divided voltage to a reference voltage, wherein an output of the comparator controls the state of the transistor.

6. The transient overvoltage protection circuit of claim 1, wherein the transistor includes a plurality of transistors connected in parallel with one another, each turned OFF by the control circuit in response to a detected overvoltage transient.

7. A transient overvoltage suppression system comprising:

a load connectable to an external power source via an input line and a return line;

a capacitor connected between the input line and the return line, in parallel with the load;

a field effect transistor (FET) connected in series on the return line; and

a control circuit connected to monitor voltage on the input line and in response to a detected transient voltage turns the FET OFF.

8. The transient voltage suppression system of claim 7, further including:

a diode connected in series on the input line.

9. The transient voltage suppression system of claim 7, wherein the control circuit controls operation of the FET with a voltage signal that is equal to or less than the magnitude of the voltage on the input line.

10. The transient voltage suppression system of claim 7, wherein the FET is an N-channel FET.

11. The transient voltage suppression system of claim 7, further including:

a test circuit connected to the control circuit that provides an input to the control circuit simulating a transient voltage condition.

12. The transient voltage suppression system of claim 7, wherein the control circuit includes:

a voltage divider network connected between the input line and the return line for providing a divided voltage that is a function of voltage between the input line and the return line; and

a comparator connected to compare the divided voltage to a reference voltage, wherein an output of the comparator controls the state of the transistor.

13. The transient voltage suppression system of claim 7, wherein the load is an internal power supply.

14. A method of providing transient voltage suppression, the method comprising:

monitoring an input line voltage provided to a load;

comparing the monitored voltage to a reference voltage to detect transient voltage spikes on the input line; and

disconnecting a return line of the load in response to a detected transient overvoltage to isolate the load from the transient voltage.

15. The method of claim 14, wherein disconnecting the return line of the load includes:

turning OFF a transistor connected in series on the return line.

16. The method of claim 15, wherein the transistor is an N-channel transistor.

17. The method of claim 14, wherein the load is an internal power supply.