Methods for Protecting Against Piracy of Integrated Circuits

• US 20100284539A1
• Filed: 03/09/2010
• Published: 11/11/2010
• Est. Priority Date: 03/09/2009
• Status: Abandoned Application

• Current Assignee: Rice University, Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Rice University, Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Markov, Igor L., Koushanfar, Farinaz, Roy, Jarrod A.
• Application Number:
  US12/720,634
• Publication Number:
  US 20100284539A1
• Time in Patent Office: Days
• US Class Current: 380/278
• CPC Class Codes: H03K 19/17768 for security
• CPC Class Codes: H04L 2209/04 Masking or blinding
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0844 with user authentication or key authentication, e.g. ElGamal, MTI, MQV-Menezes-Qu-Vanstone protocol or Diffie-Hellman protocols using implicitly-certified keys
• CPC Class Codes: H04L 9/302 involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes

Abstract

Techniques are provided for reducing the likelihood of piracy of integrated circuit design using combinational circuit locking system and activation protocol based on public-key cryptography. Every integrated circuit is to be activated with an external key, which can only be generated by an authenticator, such as the circuit designer. During circuit design, register transfer level (RTL) descriptions of the IC design are embedded with combinational logic based on a master key applied by the authenticator. That combinational logic renders at least one module of the RTL description locked, i.e., encrypted. The completed circuit design from the authenticator is sent to a fabrication lab with the combinationally locked modules. After fabrication, the circuit can only be activated when the authenticator sends an appropriate key that is used by the circuit to unlock the locked portions and thereby activate the circuit.

Claims

1. A method for locking an integrated circuit, the method comprising:

embedding an operational description of the integrated circuit design with a cryptographic key supported by a cryptographic protocol, where the integrated circuit is capable of establishing a public key and a private key pair upon start up; and

locking at least one module of the integrated circuit by applying to the at least one module a logical operator having a control signal input, where the logical operator is for unlocking the at least one module in response to the control signal input having a valid value and where the logical operator is for maintaining locking of the at least one module in response to the control signal input having an invalid value.

2. The method of claim 1, wherein the operational description is a register transfer level (RTL) description, the method further comprising:

developing a gate-level netlist from the embedded RTL description; and

locking the at least one module of the integrated circuit based on the gate-level netlist.

3. The method of claim 1, wherein the operational description is a gate-level description.

4. The method of claim 1, wherein the operational description is a high-level description.

5. The method of claim 1, further comprising the integrated circuit generating a common key that includes the valid value of the control signal input.

6. The method of claim 5, wherein the common key is randomly generated.

7. The method of claim 5, wherein the common key is generated deterministically.

8. The method of claim 5, wherein the common key is produced by a pseudorandom generator or from a serial number.

9. The method of claim 5, wherein the common key has a bit length of at least 64 bits.

10. The method of claim 1, wherein upon start-up the integrated circuit establishes the public key and the private key through a random process.

11. The method of claim 10, wherein public key and the private key are established using at least one of timing fluctuations, power fluctuations, or other fluctuations in physical parameters of the integrated circuit.

12. The method of claim 1, wherein upon start-up the integrated circuit establishes the public key and the private key deterministically.

13. The method of claim 12, wherein the public key and the private key are established by a pseudorandom generator or from a serial number.

14. The method of claim 1, wherein the integrated circuit is an application specific integrated circuit, System-on-a-chip, microprocessor, digital signal processor, graphics processing unit, central processing unit, network processor, embedded processor, or a direct memory access circuit.

15. The method of claim 1, wherein the logical operator applied to the at least one module includes an XOR gate or XNOR gate.

16. A method of activating at least one module on an integrated circuit, the method comprising:

the integrated circuit establishing a random public key and private key pair upon start up;

transmitting the random public key to an authentication source for the integrated circuit;

the authentication source sending to the integrated circuit an input key in response to receipt of the random public key, wherein the input key represents a common key for the integrated circuit and is encrypted with a private master key of the authentication source and with the received random public key;

the integrated circuit decrypting the input key using the random private key and a public master key previously received at the integrated circuit to authenticate the input key as being received from a valid authentication source; and

in response to the authentication of the input key, producing a common key that activates the at least one module on the integrated circuit.

17. The method of claim 16, further comprising establishing the random public key and the random private key using at least one true random number generator corresponding to the integrated circuit.

18. The method of claim 16, further comprising establishing the random public key and the random private key using at least one pseudorandom generator corresponding to the integrated circuit.

19. The method of claim 16, wherein the common key has a bit length of at least 64 bits.

20. The method of claim 16, wherein the input key has a bit length of at least 64 bits.

21. The method of claim 16, further comprising the authentication source randomly establishing the input key.

22. The method of claim 16, further comprising storing the random public key and the random private key pair in the integrated circuit.

23. The method of claim 16, wherein the integrated circuit is an application specific integrated circuit, System-on-a-chip, microprocessor, digital signal processor, graphics processing unit, central processing unit, network processor, embedded processor, or a direct memory access circuit.